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path: root/llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
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* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-84/+84
| | | | | | | | | Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
* Revert Patch from PhabricatorLuis Marques2019-09-171-84/+84
| | | | | | This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
* Patch from PhabricatorLuis Marques2019-09-171-84/+84
| | | | llvm-svn: 372092
* [RISCV] Custom legalize i32 operations for RV64 to reduce signed extensionsShiva Chen2019-08-061-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D65434 llvm-svn: 367960
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard ↵Alex Bradbury2019-03-301-0/+6
| | | | | | | | | | | | | | | | | | | | float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
* [RISCV] Add test cases for the lp64 ABIAlex Bradbury2019-03-121-0/+524
These are closely modeled on similar tests for the ilp32 ABI. Like those tests, we group together tests that should be common cross lp64, lp64+lp64f, and lp64+lp64f+lp64d ABIs. llvm-svn: 355899
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