bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[RISCV] Switch to the Machine Scheduler	Luis Marques	2019-09-17	1	-72/+72
\| \| \| \| \| \| \| \| \|	Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
*	Revert Patch from Phabricator	Luis Marques	2019-09-17	1	-72/+72
\| \| \| \| \| \|	This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
*	Patch from Phabricator	Luis Marques	2019-09-17	1	-72/+72
\| \| \| \|	llvm-svn: 372092
*	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard ↵	Alex Bradbury	2019-03-30	1	-0/+294
	float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352