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* R600: Expand VSELECT for all typesTom Stellard2013-07-181-0/+30
| | | | llvm-svn: 186613
* R600/SI: Add support for 64-bit loadsTom Stellard2013-07-152-0/+56
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 186339
* R600: Reapply testcase from r186178, the big endian issue should be fixed by ↵Benjamin Kramer2013-07-121-0/+12
| | | | | | r186196. llvm-svn: 186209
* R600: Remove the fpconst64.ll test which was failing on non-x86 buildbotsTom Stellard2013-07-121-12/+0
| | | | | | | I'm guessing the failure had something to do with the double precision floating point constant used in the test. llvm-svn: 186191
* R600/SI: Add support for f64 kernel argumentsTom Stellard2013-07-121-0/+9
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186182
* R600/SI: Implement select and compares for SITom Stellard2013-07-121-0/+79
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186181
* R600/SI: Add fsqrt pattern for SITom Stellard2013-07-121-0/+24
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186180
* R600/SI: Add double precision fsub pattern for SITom Stellard2013-07-121-0/+13
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186179
* R600/SI: SI support for 64bit ConstantFPTom Stellard2013-07-121-0/+12
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186178
* R600/SI: Add initial double precision support for SITom Stellard2013-07-124-0/+60
| | | | | | | Patch by: Niels Ole Salscheider Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186177
* R600/SI: Initial local memory supportMichel Danzer2013-07-102-52/+66
| | | | | | | Enough for the radeonsi driver to use it for calculating derivatives. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186012
* R600/SI: Add intrinsic for retrieving the current thread IDMichel Danzer2013-07-101-0/+16
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186010
* R600/SI: Add intrinsics for texture sampling with user derivativesMichel Danzer2013-07-101-0/+140
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 186008
* R600: Do not predicated basic block with multiple alu clauseVincent Lejeune2013-07-091-1/+1
| | | | | | | | | Test is not included as it is several 1000 lines long. To test this functionnality, a test case must generate at least 2 ALU clauses, where an ALU clause is ~110 instructions long. NOTE: This is a candidate for the stable branch. llvm-svn: 185943
* R600: Fix a rare bug where swizzle optimization returns wrong valuesVincent Lejeune2013-07-091-0/+34
| | | | llvm-svn: 185942
* R600: Fix wrong export reswizzlingVincent Lejeune2013-07-091-0/+100
| | | | llvm-svn: 185941
* R600: Use DAG lowering pass to handle fcos/fsinVincent Lejeune2013-07-092-0/+6
| | | | | NOTE: This is a candidate for the stable branch. llvm-svn: 185940
* Prefix failing commands with not to make clear they are expected to fail.Rafael Espindola2013-07-031-1/+1
| | | | llvm-svn: 185554
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-296-16/+16
| | | | llvm-svn: 185268
* R600: Add local memory support via LDSTom Stellard2013-06-281-0/+82
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185162
* R600: Add support for GROUP_BARRIER instructionTom Stellard2013-06-281-0/+24
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 185161
* R600: Remove alu-split.ll testTom Stellard2013-06-271-851/+0
| | | | | | | | | | | | | | | The purpose of this test was to check boundary conditions for the size of an ALU clause. This test is very sensitive to changes to the optimizer or scheduler, because it requires an exact number of ALU instructions in order to remain valid. It's not good to have a test this sensitive, because it is confusing to developers who implement optimizations and then 'break' the test. I'm not sure if there is a good way to test these limits using lit, but if I can come up with replacement test that isn't as sensitive I'll add it back to the tree. llvm-svn: 185084
* R600: Use new getNamedOperandIdx function generated by TableGenTom Stellard2013-06-251-0/+59
| | | | llvm-svn: 184880
* R600: Add v2i32 test for vselectAaron Watry2013-06-251-6/+20
| | | | | | | | | | | | | Note: Only adding test for evergreen, not SI yet. When I attempted to expand vselect for SI, I got the following: llc: /home/awatry/src/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp:522: llvm::SDValue llvm::DAGTypeLegalizer::PromoteIntRes_SETCC(llvm::SDNode*): Assertion `SVT.isVector() == N->getOperand(0).getValueType().isVector() && "Vector compare must return a vector result!"' failed. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184847
* R600/SI: Expand xor v2i32/v4i32Aaron Watry2013-06-251-7/+33
| | | | | | | Add test cases for both vector sizes on SI and also add v2i32 test for EG. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184846
* R600: Add v2i32 test for setcc on evergreenAaron Watry2013-06-251-3/+22
| | | | | | | | | | No test/expansion for SI has been added yet. Attempts to expand this operation for SI resulted in a stacktrace in (IIRC) LegalizeIntegerTypes which was complaining about vector comparisons being required to return a vector type. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184845
* R600/SI: Expand urem of v2i32/v4i32 for SIAaron Watry2013-06-251-4/+23
| | | | | | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UREM produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184844
* R600/SI: Expand udiv v[24]i32 for SI and v2i32 for EGAaron Watry2013-06-251-3/+22
| | | | | | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Note: I followed the guidance of the v4i32 EG check... UDIV produces really complex code, so let's just check that the instruction was lowered successfully. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184843
* R600/SI: Expand ashr of v2i32/v4i32 for SIAaron Watry2013-06-251-7/+34
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184842
* R600/SI: Expand srl of v2i32/v4i32 for SIAaron Watry2013-06-251-7/+35
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184841
* R600/SI: Expand shl of v2i32/v4i32 for SIAaron Watry2013-06-251-7/+34
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184840
* R600/SI: Expand or of v2i32/v4i32 for SIAaron Watry2013-06-251-7/+34
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184839
* R600/SI: Expand mul of v2i32/v4i32 for SIAaron Watry2013-06-251-6/+32
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184838
* R600/SI: Expand and of v2i32/v4i32 for SIAaron Watry2013-06-251-6/+31
| | | | | | | Also add lit test for both cases on SI, and v2i32 for evergreen. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 184837
* R600/SI: Report unaligned memory accesses as legal for > 32-bit typesTom Stellard2013-06-251-0/+32
| | | | | | | | | | | In reality, some unaligned memory accesses are legal for 32-bit types and smaller too, but it all depends on the address space. Allowing unaligned loads/stores for > 32-bit types is mainly to prevent the legalizer from splitting one load into multiple loads of smaller types. https://bugs.freedesktop.org/show_bug.cgi?id=65873 llvm-svn: 184822
* R600: Add support for i32 loads from the constant address space on CaymanTom Stellard2013-06-251-0/+1
| | | | | Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 184821
* R600/SI: Add support for v4i32 and v4f32 kernel argsTom Stellard2013-06-251-6/+10
| | | | | Tested-By: Aaron Watry <awatry@gmail.com> llvm-svn: 184820
* R600: Fix typo in R600Schedule.tdTom Stellard2013-06-251-0/+34
| | | | | | | | | | | | | | | | This should only make a difference in programs that use a lot of the vector ALU instructions like BFI_INT and BIT_ALIGN. There is a slight improvement in the phatk bitcoin mining kernel with this patch on Evergreen (vector size == 1): Before: 1173 Instruction Groups / 9520 dwords After: 1167 Instruction Groups / 9510 dwords Reviewed-by: Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184819
* R600/SI: Expand sub for v2i32 and v4i32 for SITom Stellard2013-06-201-6/+31
| | | | | | | | | | Also add a v2i32 test to the existing v4i32 test. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> llvm-svn: 184482
* R600/SI: Expand add for v2i32 and v4i32Tom Stellard2013-06-201-6/+31
| | | | | | | | | | | Also add SI tests to existing file and a v2i32 test for both R600 and SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> llvm-svn: 184481
* R600: Expand v2i32 load/store instead of custom loweringTom Stellard2013-06-201-0/+6
| | | | | | | | | | | | | The custom lowering causes llc to crash with a segfault. Ideally, the custom lowering can be fixed, but this allows programs which load/store v2i32 to work without crashing. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry<awatry@gmail.com> llvm-svn: 184480
* R600: PV stores Reg id, not indexVincent Lejeune2013-06-171-0/+50
| | | | llvm-svn: 184117
* R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen.Vincent Lejeune2013-06-171-0/+44
| | | | | | | Fixes rv7x0 bug in Heaven reported here: https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 184116
* R600: Add SI load support for v[24]i32 and store for v2i32Tom Stellard2013-06-151-0/+19
| | | | | | | | | | | Also add a seperate vector lit test file, since r600 doesn't seem to handle v2i32 load/store yet, but we can test both for SI. Patch by: Aaron Watry Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Aaron Watry <awatry@gmail.com> llvm-svn: 184021
* R600: Use correct encoding for Vertex Fetch instructions on CaymanTom Stellard2013-06-141-0/+25
| | | | | Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184016
* R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on CaymanTom Stellard2013-06-141-0/+3
| | | | | | | | | We were using RAT_INST_STORE_RAW, which seemed to work, but the docs say this instruction doesn't exist for Cayman, so it's probably safer to use a documented instruction instead. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 184015
* R600: Anti dep better handled in tex clauseVincent Lejeune2013-06-071-0/+24
| | | | llvm-svn: 183592
* R600: Fix calculation of stack offset in AMDGPUFrameLoweringTom Stellard2013-06-071-0/+33
| | | | | | | | | We weren't computing structure size correctly and we were relying on the original alloca instruction to compute the offset, which isn't always reliable. Reviewed-by: Vincent Lejeune <vljn@ovi.com> llvm-svn: 183568
* R600: Fix the fetch limits for R600 generation GPUsTom Stellard2013-06-072-0/+129
| | | | | | | | Reviewed-by: Vincent Lejeune <vljn@ovi.com> https://bugs.freedesktop.org/show_bug.cgi?id=64257 llvm-svn: 183560
* R600: Add a pass that merge Vector RegisterVincent Lejeune2013-06-051-0/+30
| | | | | | | Previously commited @183279 but tests were failing, reverted @183286 It was broken because @183336 was missing, now it's there. llvm-svn: 183343
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