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* R600/SI: Add support for i64 bitwise orTom Stellard2013-10-231-4/+17
| | | | llvm-svn: 193213
* R600/SI: Use S_LOAD_DWORD instructions for v8i32 and v16i32Tom Stellard2013-10-231-5/+10
| | | | llvm-svn: 193212
* R600: Simplify handling of private address spaceTom Stellard2013-10-221-0/+39
| | | | | | | | | | | | | | | | | | The AMDGPUIndirectAddressing pass was previously responsible for lowering private loads and stores to indirect addressing instructions. However, this pass was buggy and way too complicated. The only advantage it had over the new simplified code was that it saved one instruction per direct write to private memory. This optimization likely has a minimal impact on performance, and we may be able to duplicate it using some other transformation. For the private address space, we now: 1. Lower private loads/store to Register(Load|Store) instructions 2. Reserve part of the register file as 'private memory' 3. After regalloc lower the Register(Load|Store) instructions to MOV instructions that use indirect addressing. llvm-svn: 193179
* Fix CodeGen for vectors of pointers with address spaces.Matt Arsenault2013-10-211-0/+30
| | | | llvm-svn: 193112
* Fix CodeGen for different size address space GEPsMatt Arsenault2013-10-211-0/+10
| | | | llvm-svn: 193111
* R600: Fix a crash in the AMDILCFGStructurizerTom Stellard2013-10-161-0/+83
| | | | | | | | | | We were calling llvm_unreachable() when failing to optimize the branch into if case. However, it is still possible for us to structurize the CFG by duplicating blocks even if this optimization fails. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192813
* R600: improve dump of S_WAITCNTVincent Lejeune2013-10-131-0/+37
| | | | llvm-svn: 192557
* R600: Use masked read sel for texture instructionsVincent Lejeune2013-10-131-8/+7
| | | | llvm-svn: 192554
* R600: fix swizzle exportVincent Lejeune2013-10-132-1/+147
| | | | llvm-svn: 192553
* R600: Add scalar i32 add testMatt Arsenault2013-10-111-0/+16
| | | | llvm-svn: 192501
* Use CHECK-LABELMatt Arsenault2013-10-111-8/+8
| | | | llvm-svn: 192500
* R600: Fix trunc i64 to i32 on SIMatt Arsenault2013-10-101-0/+12
| | | | llvm-svn: 192375
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-1084-86/+86
| | | | | | | | | | We can't enable the verifier for tests with SI_IF and SI_ELSE, because these instructions are always followed by a COPY which copies their result to the next basic block. This violates the machine verifier's rule that non-terminators can not folow terminators. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 192366
* Add some xfaild R600 tests.Matt Arsenault2013-10-083-0/+47
| | | | | | These are bugs to fix later. llvm-svn: 192212
* R600: add a pass that merges clauses.Vincent Lejeune2013-10-013-5/+6
| | | | llvm-svn: 191790
* R600: Put PRED_X instruction in its own clauseVincent Lejeune2013-10-014-6/+1182
| | | | llvm-svn: 191789
* R600: Enable -verify-machineinstrs in some tests.Vincent Lejeune2013-10-015-5/+5
| | | | llvm-svn: 191788
* TBAA: update tbaa format from scalar format to struct-path aware format.Manman Ren2013-09-303-17/+19
| | | | llvm-svn: 191690
* TBAA: remove !tbaa from testing cases when they are not needed.Manman Ren2013-09-303-38/+29
| | | | llvm-svn: 191689
* R600: Fix handling of NAN in comparison instructionsTom Stellard2013-09-287-61/+87
| | | | | | | | We were completely ignoring the unorder/ordered attributes of condition codes and also incorrectly lowering seto and setuo. Reviewed-by: Vincent Lejeune<vljn at ovi.com> llvm-svn: 191603
* R600: Move code handling literal folding into R600ISelLowering.Vincent Lejeune2013-09-121-0/+16
| | | | llvm-svn: 190644
* R600: Move fabs/fneg/sel folding logic into PostProcessIselVincent Lejeune2013-09-121-0/+18
| | | | | | | This move makes possible to correctly handle multiples instructions from a single pattern. llvm-svn: 190643
* R600/SI: expose TBUFFER_STORE_FORMAT_* for OpenGL transform feedbackTom Stellard2013-09-121-0/+44
| | | | | | | | | | | | | For _XYZ, the type of VDATA is v4i32, because v3i32 doesn't exist. The ADDR64 bit is not exposed. A simpler intrinsic that doesn't take a resource descriptor might be nicer. The maximum number of input SGPRs is bumped to 17. Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190575
* R600: Add support for LDS atomic subtractAaron Watry2013-09-061-0/+23
| | | | | | Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 190200
* Teach CodeGenPrepare about address spacesMatt Arsenault2013-09-061-0/+30
| | | | llvm-svn: 190112
* R600: Fix i64 to i32 trunc on SIMatt Arsenault2013-09-051-0/+19
| | | | llvm-svn: 190091
* R600: Add support for local memory atomic addTom Stellard2013-09-051-0/+23
| | | | llvm-svn: 190080
* R600: Expand SELECT nodes rather than custom lowering themTom Stellard2013-09-051-0/+46
| | | | llvm-svn: 190079
* R600: Fix incorrect LDS size calculationTom Stellard2013-09-051-0/+26
| | | | | | | GlobalAdderss nodes that appeared in more than one basic block were being counted twice. llvm-svn: 190078
* R600/SI: Don't emit S_WQM_B64 instruction for compute shadersTom Stellard2013-09-052-0/+14
| | | | llvm-svn: 190077
* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+38
| | | | llvm-svn: 189981
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-0424-127/+239
| | | | llvm-svn: 189980
* R600: Remove fmul.v4f32.ll test which is redundant with fmul.llVincent Lejeune2013-09-041-15/+0
| | | | llvm-svn: 189978
* R600/SI: Enable local-memory-two-objects lit testMichel Danzer2013-08-271-12/+17
| | | | | Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 189334
* SelectionDAG: Remove unnecessary uses of TargetLowering::getPointerTy()Tom Stellard2013-08-261-0/+140
| | | | | | | | | | | | If we have a binary operation like ISD:ADD, we can set the result type equal to the result type of one of its operands rather than using TargetLowering::getPointerTy(). Also, any use of DAG.getIntPtrConstant(C) as an operand for a binary operation can be replaced with: DAG.getConstant(C, OtherOperand.getValueType()); llvm-svn: 189227
* R600: Add support for vector local memory loadsTom Stellard2013-08-261-0/+14
| | | | llvm-svn: 189226
* R600: Add support for i8 and i16 local memory loadsTom Stellard2013-08-261-0/+78
| | | | llvm-svn: 189225
* SelectionDAG: Use correct pointer size when splitting vector storesTom Stellard2013-08-261-0/+15
| | | | llvm-svn: 189224
* R600: Add support for i8 and i16 local memory storesTom Stellard2013-08-261-0/+18
| | | | llvm-svn: 189223
* R600: Add support for v4i32 and v2i32 local storesTom Stellard2013-08-261-0/+52
| | | | llvm-svn: 189222
* SelectionDAG: Use correct pointer size when lowering function arguments v2Tom Stellard2013-08-261-0/+42
| | | | | | | | | | | | | | | | This adds minimal support to the SelectionDAG for handling address spaces with different pointer sizes. The SelectionDAG should now correctly lower pointer function arguments to the correct size as well as generate the correct code when lowering getelementptr. This patch also updates the R600 DataLayout to use 32-bit pointers for the local address space. v2: - Add more helper functions to TargetLoweringBase - Use CHECK-LABEL for tests llvm-svn: 189221
* Update to remove the no-frame-pointer-elim-non-leaf flag if it was set to ↵Bill Wendling2013-08-222-2/+2
| | | | | | 'false'. llvm-svn: 189068
* R600/SI: Fix another case of illegal VGPR to SGPR copyTom Stellard2013-08-221-3/+142
| | | | | | | | This fixes a crash in Unigine Tropics. https://bugs.freedesktop.org/show_bug.cgi?id=68389 llvm-svn: 189057
* SelectionDAG: Make sure stores are always added to the LegalizedNodes listTom Stellard2013-08-211-0/+20
| | | | | | | | | | | | | | | | When truncated vector stores were being custom lowered in VectorLegalizer::LegalizeOp(), the old (illegal) and new (legal) node pair was not being added to LegalizedNodes list. Instead of the legalized result being passed to VectorLegalizer::TranslateLegalizeResult(), the result was being passed back into VectorLegalizer::LegalizeOp(), which ended up adding a (new, new) pair to the list instead. This was causing an assertion failure when a custom lowered truncated vector store was the last instruction a basic block and the VectorLegalizer was unable to find it in the LegalizedNodes list when updating the DAG root. llvm-svn: 188953
* R600: Expand vector FRINT opsTom Stellard2013-08-161-0/+54
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188598
* R600: Expand vector FFLOOR opsTom Stellard2013-08-161-0/+54
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188597
* R600: Expand vector float operations for both SI and R600Tom Stellard2013-08-164-75/+110
| | | | | Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 188596
* R600/SI: Add pattern for xor of i1Michel Danzer2013-08-161-0/+17
| | | | | | | Fixes two recent piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188559
* R600/SI: Fix broken encoding of DS_WRITE_B32Michel Danzer2013-08-161-2/+2
| | | | | | | | | | | | | | The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused it to corrupt the encoding of that by clobbering the first operand with the second one. Undo that damage and only apply the SMRD logic to that. Fixes some derivates related piglit regressions with radeonsi. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 188558
* Revert "R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions"Tom Stellard2013-08-161-2/+2
| | | | | | | This reverts commit a6a39ced095c2f453624ce62c4aead25db41a18f. This is the wrong version of this fix. llvm-svn: 188523
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