summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/R600
Commit message (Collapse)AuthorAgeFilesLines
...
* R600: Take alignment into account when calculating the stack offsetTom Stellard2014-01-221-0/+31
| | | | llvm-svn: 199826
* R600: Add support for global addresses with constant initializersTom Stellard2014-01-221-0/+41
| | | | llvm-svn: 199825
* R600: Begin private memory at the second GPR.Tom Stellard2014-01-221-0/+25
| | | | | | | This way private memory does not over-write work group information stored in GPRs 0 and 1. llvm-svn: 199824
* R600/SI: Add support for i8 and i16 private loads/storesTom Stellard2014-01-222-14/+59
| | | | llvm-svn: 199823
* Fix broken CHECK lines.Benjamin Kramer2014-01-116-10/+10
| | | | llvm-svn: 199016
* R600: Allow ftruncTom Stellard2013-12-201-0/+13
| | | | | | | | | | | v2: Add ftrunc->TRUNC pattern instead of replacing int_AMDGPU_trunc v3: move ftrunc pattern next to TRUNC definition, it's available since R600 Patch By: Jan Vesely Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 197783
* Add REQUIRES:asserts to 3 tests in llvm/test/CodeGen/R600 added in r192212.NAKAMURA Takumi2013-12-193-0/+3
| | | | | | They are failing in assertions. llvm-svn: 197669
* R600/SI: Make private pointers be 32-bit.Matt Arsenault2013-12-191-0/+31
| | | | | | | | Different sized address spaces should theoretically work most of the time now, and since 64-bit add is currently disabled, using more 32-bit pointers fixes some cases. llvm-svn: 197659
* R600/SI: Minor improvements to test.Matt Arsenault2013-12-141-5/+15
| | | | | | Use CHECK-LABEL, add an i64 version, check store instructions. llvm-svn: 197293
* R600/SI: Add i64 cmp testsMatt Arsenault2013-12-101-0/+92
| | | | llvm-svn: 196960
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-0/+59
| | | | llvm-svn: 196923
* R600: Fix input modifiers lost for CaymanVincent Lejeune2013-12-101-0/+26
| | | | llvm-svn: 196922
* Add a RequireStructuredCFG Field to TargetMachine.Vincent Lejeune2013-12-071-1/+1
| | | | llvm-svn: 196634
* R600/SI: Add comments for number of used registers.Matt Arsenault2013-12-051-0/+20
| | | | llvm-svn: 196467
* R600: Workaround for cayman loop bugVincent Lejeune2013-12-021-0/+32
| | | | llvm-svn: 196121
* R600: Expand vector FABSTom Stellard2013-11-271-2/+34
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195881
* R600/SI: Implement spilling of SGPRs v5Tom Stellard2013-11-271-3/+877
| | | | | | | | | | | | | | | | | | | | | | | | | | SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195880
* R600/SI: Use SGPR_32 register class for 32-bit SMRD outputsTom Stellard2013-11-271-0/+692
| | | | | | | | Writing to the M0 register from an SMRD instruction hangs the GPU, so we need to use the SGPR_32 register class, which does not include M0. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195879
* R600: Add support for ISD::FROUNDTom Stellard2013-11-271-0/+41
| | | | | NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195878
* R600/SI: Fixing handling of condition codesTom Stellard2013-11-222-9/+577
| | | | | | | | We were ignoring the ordered/onordered bits and also the signed/unsigned bits of condition codes when lowering the DAG to MachineInstrs. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195514
* SelectionDAG: Optimize expansion of vec_type = BITCAST scalar_typeTom Stellard2013-11-221-0/+15
| | | | | | | | | The legalizer can now do this type of expansion for more type combinations without loading and storing to and from the stack. NOTE: This is a candidate for the 3.4 branch. llvm-svn: 195398
* R600/SI: Fix moveToVALU when the first operand is VSrc.Matt Arsenault2013-11-181-11/+10
| | | | | | | Moving into a VSrc doesn't always work, since it could be replaced with an SGPR later. llvm-svn: 195042
* R600/SI: Fix multiple SGPR reads when using VCC.Matt Arsenault2013-11-181-3/+18
| | | | | | | No other SGPR operands are allowed, so if VCC is used, move the other to a VGPR. llvm-svn: 195041
* R600/SI: Implement add i64, but do not yet enable.Matt Arsenault2013-11-181-0/+45
| | | | | | | | Test doesn't actually check the output. I need to fix add i64 being matched for the addressing calculations. llvm-svn: 195040
* R600/SI: Move patterns to match add / sub to scalar instructionsMatt Arsenault2013-11-184-20/+24
| | | | llvm-svn: 195034
* R600: Enable the IR structurizer by defaultTom Stellard2013-11-183-3/+3
| | | | llvm-svn: 195031
* R600: Fix a crash in the AMDILCFGStrucurizerTom Stellard2013-11-181-0/+62
| | | | | | | The ifPatternMatch() function was not correctly reporting the number of matches in some cases. llvm-svn: 195030
* R600/SI: Fix illegal VGPR->SGPR copy inside of loopTom Stellard2013-11-181-0/+31
| | | | llvm-svn: 195026
* R600/SI: Fix another case of illegal VGPR->SGPR copyTom Stellard2013-11-181-0/+26
| | | | llvm-svn: 195025
* Use right address space pointer sizeMatt Arsenault2013-11-171-0/+11
| | | | llvm-svn: 194940
* Fix assert on unaligned access to global with different address space size.Matt Arsenault2013-11-161-1/+23
| | | | llvm-svn: 194934
* Fix codegen for null different sized pointer.Matt Arsenault2013-11-161-0/+11
| | | | llvm-svn: 194932
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+27
| | | | llvm-svn: 194927
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+46
| | | | | | This fixes a crash with GNOME settings manager. llvm-svn: 194836
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-151-0/+42
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. llvm-svn: 194783
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-152-3/+104
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add testcase for problem I ran intoMatt Arsenault2013-11-141-0/+18
| | | | | | with the older version of the moveToVALU changes. llvm-svn: 194682
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-134-20/+27
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-138-109/+128
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* R600: Fix selection failure on EXTLOADMatt Arsenault2013-11-131-0/+51
| | | | llvm-svn: 194547
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-1253-280/+279
| | | | | | | | | | | | | | | | | | | | | | | Print the range of registers used with a single letter prefix. This better matches what the shader compiler produces and is overall less obnoxious than concatenating all of the subregister names together. Instead of SGPR0, it will print s0. Instead of SGPR0_SGPR1, it will print s[0:1] and so on. There doesn't appear to be a straightforward way to get the actual register info in the InstPrinter, so this parses the generated name to print with the new syntax. The required test changes are pretty nasty, and register matching regexes are now worse. Since there isn't a way to add to a variable in FileCheck, some of the tests now don't check the exact number of registers used, but I don't think that will be a real problem. llvm-svn: 194443
* R600/SI: Add test that fails due to requiring i64 mul for pointersMatt Arsenault2013-11-111-0/+18
| | | | llvm-svn: 194433
* R600: Use function inputs to represent data stored in gprVincent Lejeune2013-11-1125-280/+246
| | | | llvm-svn: 194425
* R600: Fix LowerUDIVREMVincent Lejeune2013-11-061-4/+17
| | | | llvm-svn: 194153
* Fix CodeGen for unaligned loads with address spacesMatt Arsenault2013-10-301-0/+19
| | | | llvm-svn: 193721
* R600: Custom lower f32 = uint_to_fp i64Tom Stellard2013-10-301-4/+19
| | | | llvm-svn: 193701
* R600/SI: Add compute support for CI v2Tom Stellard2013-10-291-7/+11
| | | | | | | | v2: - Fix LDS size calculation Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 193621
* R600: Expand vector FSQRT opsTom Stellard2013-10-291-0/+54
| | | | llvm-svn: 193620
* R600/SI: fix MIMG writemask adjustementTom Stellard2013-10-231-0/+93
| | | | | | | | | | | | This fixes piglit: - shaders/glsl-fs-texture2d-masked - shaders/glsl-fs-texture2d-masked-4 Patch by: Marek Olšák Signed-off-by: Marek Olšák <marek.olsak@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 193222
* R600: Fix handling of vector kernel argumentsTom Stellard2013-10-235-115/+502
| | | | | | | | | | The SelectionDAGBuilder was promoting vector kernel arguments to legal types, but this won't work for R600 and SI since kernel arguments are stored in memory and can't be promoted. In order to handle vector arguments correctly we need to look at the original types from the LLVM IR function. llvm-svn: 193215
OpenPOWER on IntegriCloud