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* R600: Expand i64 ISD:SUBTom Stellard2014-05-051-18/+37
| | | | llvm-svn: 208005
* R600: Expand vector sin and cos.Tom Stellard2014-05-022-22/+65
| | | | | | | | v2: move code to AMDGPUISelLowering.cpp squash with tests (both EG and SI) Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 207845
* R600: Expand TruncStore i64 -> {i16,i8}Tom Stellard2014-05-021-0/+40
| | | | llvm-svn: 207844
* R600/SI: Fix verifier error with pseudo store instructions.Matt Arsenault2014-05-013-4/+4
| | | | | | | | Use i32 instead of specifying SReg_32. When this is the pseudo INDIRECT_BASE_ADDR, this would give a bogus verifier error. llvm-svn: 207770
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-301-0/+39
| | | | | | | | | We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-0/+28
| | | | llvm-svn: 207660
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-2925-25/+25
| | | | | | | | | | | | | | | | SI_IF and SI_ELSE are terminators which also produce a value. For these instructions ISel always inserts a COPY to move their value to another basic block. This COPY ends up between SI_(IF|ELSE) and the S_BRANCH* instruction at the end of the block. This breaks MachineBasicBlock::getFirstTerminator() and also the machine verifier which assumes that terminators are grouped together at the end of blocks. To solve this we coalesce the copy away right after ISel to make sure there are no instructions in between terminators at the end of blocks. llvm-svn: 207591
* R600/SI: Only select SALU instructions in the entry or exit blockTom Stellard2014-04-291-0/+27
| | | | | | | | SALU instructions ignore control flow, so it is not always safe to use them within branches. This is a partial solution to this problem until we can come up with something better. llvm-svn: 207590
* R600: optimize the UDIVREM 64 algorithmTom Stellard2014-04-291-0/+84
| | | | | | | | | | | | | | | | This is a squash of several optimization commits: - calculate DIV_Lo and DIV_Hi separately - use BFE_U32 if we are operating on 32bit values - use precomputed constants instead of shifting in UDVIREM - skip the first 32 iterations of udivrem v2: Check whether BFE is supported before using it Patch by: Jan Vesely Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 207589
* R600: Add a test that used to be broken that I forgot to addMatt Arsenault2014-04-231-0/+29
| | | | llvm-svn: 207017
* R600: Emit error instead of unreachable on function callMatt Arsenault2014-04-221-0/+33
| | | | llvm-svn: 206904
* R600: Make sign_extend_inreg legal.Matt Arsenault2014-04-221-0/+13
| | | | | | Don't know why I didn't just do this in the first place. llvm-svn: 206862
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-181-11/+40
| | | | | | | | Use scalar BFE with constant shift and offset when possible. This is complicated by the fact that the scalar version packs the two operands of the vector version into one. llvm-svn: 206558
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-22/+27
| | | | llvm-svn: 206547
* R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIRTom Stellard2014-04-182-6/+10
| | | | llvm-svn: 206541
* R600/SI: Stop using i128 as the resource descriptor typeTom Stellard2014-04-171-0/+26
| | | | | | | | | Having i128 as a legal type complicates the legalization phase. v4i32 is already a legal type, so we will use that instead. This fixes several piglit tests. llvm-svn: 206500
* R600/SI: f64 frint is legal on CIMatt Arsenault2014-04-172-27/+59
| | | | llvm-svn: 206475
* R600/SI: Fix zext from i1 to i64Matt Arsenault2014-04-172-0/+28
| | | | llvm-svn: 206437
* R600: Extend r600 sign_extend_inreg tests for EGMatt Arsenault2014-04-161-22/+85
| | | | | | Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 206349
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-1517-85/+85
| | | | | | | | | Print in decimal for inline immediates, and hex otherwise. Use hex always for offsets in addressing offsets. This approximately matches what the shader compiler does. llvm-svn: 206335
* R600/SI: Fix loads of i1Matt Arsenault2014-04-151-0/+107
| | | | llvm-svn: 206330
* SelectionDAG: Use helper function to improve legalization of ISD::MULTom Stellard2014-04-113-42/+63
| | | | | | | | The TargetLowering::expandMUL() helper contains lowering code extracted from the DAGTypeLegalizer and allows the SelectionDAGLegalizer to expand more ISD::MUL patterns without having to use a library call. llvm-svn: 206037
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-0/+18
| | | | llvm-svn: 205837
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+26
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-075-68/+100
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Correct opcode for BFE_INTTom Stellard2014-04-031-1/+2
| | | | | | | | | | | Acording to AMD documentation, the correct opcode for BFE_INT is 0x5, not 0x4 Fixes Arithm/Absdiff.Mat/3 OpenCV test Patch by: Bruno Jiménez llvm-svn: 205562
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-032-4/+5
| | | | llvm-svn: 205561
* TargetLibraryInfo: Disable memcpy and memset on R600Tom Stellard2014-04-021-0/+54
| | | | | | There are no implementations of these for R600. llvm-svn: 205455
* Fix missing RUN line in testMatt Arsenault2014-04-011-0/+1
| | | | llvm-svn: 205341
* Make isSetCCEquivalent respect the TargetBooleanContentsMatt Arsenault2014-04-011-0/+29
| | | | llvm-svn: 205336
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-312-0/+30
| | | | llvm-svn: 205242
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-314-0/+161
| | | | llvm-svn: 205236
* R600/SI: Lower i64 SELECT by bitcasting to a vector typeTom Stellard2014-03-311-0/+3
| | | | | | | This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op. llvm-svn: 205187
* R600: Implement isZExtFree.Matt Arsenault2014-03-275-6/+46
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-271-0/+21
| | | | llvm-svn: 204945
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+14
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* R600: Add failing testcase for <3 x i32> stores.Matt Arsenault2014-03-252-0/+12
| | | | | | | This is supposed to have the same store size and alignment as <4 x i32>, but currently is split into a 64-bit and 32-bit store. llvm-svn: 204729
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-5/+5
| | | | | | | Check the register class of each operand individually to avoid an extra copy to a vgpr. llvm-svn: 204662
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-241-33/+60
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-7/+26
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-241-5/+18
| | | | llvm-svn: 204658
* R600/SI: Fix 64-bit private loads.Matt Arsenault2014-03-241-8/+52
| | | | llvm-svn: 204630
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-217-38/+119
| | | | | | | Some of them also had the pattern on both, so this removes the duplication. llvm-svn: 204492
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-1/+7
| | | | llvm-svn: 204476
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-0/+42
| | | | llvm-svn: 204475
* R600/SI: Add support for 64-bit LDS writesMatt Arsenault2014-03-191-0/+75
| | | | llvm-svn: 204274
* R600/SI: Add support for 64-bit LDS loads.Matt Arsenault2014-03-191-0/+83
| | | | | | | v2: -Use correct opcode for DS_READ_64 llvm-svn: 204273
* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-194-11/+75
| | | | llvm-svn: 204272
* R600/SI: Fix test checking wrong instruction operand.Matt Arsenault2014-03-191-1/+1
| | | | | | The source and destination happen to be the same register. llvm-svn: 204271
* R600/SI: Don't display the GDS bit.Matt Arsenault2014-03-195-11/+11
| | | | | | | | It isn't actually used now, and probably never will be, plus it makes tests less annoying. I also think SC prints GDS instructions as a separate instruction name. llvm-svn: 204270
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