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* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-131-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a weak variant of the cmpxchg operation, as described in C++11. A cmpxchg instruction with this modifier is permitted to fail to store, even if the comparison indicated it should. As a result, cmpxchg instructions must return a flag indicating success in addition to their original iN value loaded. Thus, for uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The second flag is 1 when the store succeeded. At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been added as the natural representation for the new cmpxchg instructions. It is a strong cmpxchg. By default this gets Expanded to the existing ATOMIC_CMP_SWAP during Legalization, so existing backends should see no change in behaviour. If they wish to deal with the enhanced node instead, they can call setOperationAction on it. Beware: as a node with 2 results, it cannot be selected from TableGen. Currently, no use is made of the extra information provided in this patch. Test updates are almost entirely adapting the input IR to the new scheme. Summary for out of tree users: ------------------------------ + Legacy Bitcode files are upgraded during read. + Legacy assembly IR files will be invalid. + Front-ends must adapt to different type for "cmpxchg". + Backends should be unaffected by default. llvm-svn: 210903
* R600/SI: Fix selection error on i64 rotl / rotr.Matt Arsenault2014-06-133-26/+129
| | | | | | Evergreen is still broken due to missing shl_parts. llvm-svn: 210885
* R600: Mostly remove remaining AMDIL intrinsics.Matt Arsenault2014-06-121-10/+22
| | | | | | | | | Delete all unused ones, and add new AMDGPU named intrinsics for the ones that are. Handle the old AMDIL names for comptability (although remove their GCCBuiltin names) and add tests since there weren't any for these before. llvm-svn: 210827
* Revert "SelectionDAG: Enable (and (setcc x), (setcc y)) -> (setcc (and x, ↵Tom Stellard2014-06-121-0/+1
| | | | | | | | | y)) for vectors" This reverts commit r210540, adds a testcase for the regression it caused, and marks the R600 test it was supposed to fix as XFAIL. llvm-svn: 210792
* R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*Matt Arsenault2014-06-122-6/+22
| | | | | | | There is not such thing as a 0-data ds instruction, and the data operand needs to be a vgpr set to something meaningful. llvm-svn: 210756
* R600/SI: Fix bitcast between v2i32 and f64Matt Arsenault2014-06-111-5/+25
| | | | | | | | | | This is the same problem fixed in r210664 for more types. The test passes without this fix. For some reason I'm only hitting this when creating selects lowered to v2i32 selects. llvm-svn: 210692
* R600/SI: Add common 64-bit LDS atomicsMatt Arsenault2014-06-112-0/+262
| | | | llvm-svn: 210680
* R600/SI: Add 32-bit LDS atomic cmpxchgMatt Arsenault2014-06-111-0/+16
| | | | llvm-svn: 210678
* R600/SI: Use LDS atomic inc / decMatt Arsenault2014-06-111-0/+38
| | | | llvm-svn: 210677
* R600/SI: Add other LDS atomic operationsMatt Arsenault2014-06-111-0/+208
| | | | llvm-svn: 210676
* R600/SI: Fix backwards names for local atomic instructions.Matt Arsenault2014-06-112-8/+8
| | | | | | | The manual lists them as *_RTN_U32, not *_U32_RTN, which is more consistent with how every other sized instruction is named. llvm-svn: 210674
* R600/SI: Refactor local atomics.Matt Arsenault2014-06-112-30/+60
| | | | | | | Use patterns that will also match the immediate offset to match the normal read / writes. llvm-svn: 210673
* R600/SI: Use v_cvt_f32_ubyte* instructionsMatt Arsenault2014-06-113-0/+227
| | | | | | | This eliminates extra extract instructions when loading an i8 vector to a float vector. llvm-svn: 210666
* R600/SI: Fix selection failure on scalar_to_vectorMatt Arsenault2014-06-112-5/+99
| | | | | | | | | | | There seem to be only 2 places that produce these, and it's kind of tricky to hit them. Also fixes failure to bitcast between i64 and v2f32, although this for some reason wasn't actually broken in the simple bitcast testcase, but did in the scalar_to_vector one. llvm-svn: 210664
* R600: Use BCNT_INT for evergreenMatt Arsenault2014-06-101-0/+51
| | | | llvm-svn: 210569
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+91
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-0/+203
| | | | llvm-svn: 210567
* R600: Handle fcopysignMatt Arsenault2014-06-102-0/+87
| | | | llvm-svn: 210564
* R600/SI: Handle sign_extend and zero_extend to i64 with patterns.Matt Arsenault2014-06-101-7/+56
| | | | llvm-svn: 210563
* SelectionDAG: Expand SELECT_CC to SELECT + SETCCTom Stellard2014-06-102-6/+10
| | | | | | | | This consolidates code from the Hexagon, R600, and XCore targets. No functionality change intended. llvm-svn: 210539
* Reduce verbiage of lit.local.cfg filesAlp Toker2014-06-091-2/+1
| | | | | | We can just split targets_to_build in one place and make it immutable. llvm-svn: 210496
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-092-1/+41
| | | | llvm-svn: 210476
* R600: Fix selection failure for vector bswapMatt Arsenault2014-06-091-0/+50
| | | | llvm-svn: 210475
* R600: Add more and testcasesMatt Arsenault2014-06-091-18/+88
| | | | llvm-svn: 210453
* Allow aliases to be unnamed_addr.Rafael Espindola2014-06-065-8/+8
| | | | | | | | | | | | | | | | | | Alias with unnamed_addr were in a strange state. It is stored in GlobalValue, the language reference talks about "unnamed_addr aliases" but the verifier was rejecting them. It seems natural to allow unnamed_addr in aliases: * It is a property of how it is accessed, not of the data itself. * It is perfectly possible to write code that depends on the address of an alias. This patch then makes unname_addr legal for aliases. One side effect is that the syntax changes for a corner case: In globals, unnamed_addr is now printed before the address space. llvm-svn: 210302
* R600: Fix test. Using wrong check prefix.Matt Arsenault2014-06-051-21/+21
| | | | llvm-svn: 210244
* R600/SI: Match rsq instructionsMatt Arsenault2014-06-051-0/+26
| | | | llvm-svn: 210226
* R600/SI: Fix [s|u]int_to_fp for i1Matt Arsenault2014-05-314-29/+124
| | | | llvm-svn: 209971
* R600: Try to convert BFE back to standard bit ops when possible.Matt Arsenault2014-05-224-11/+276
| | | | | | | This allows existing DAG combines to work on them, and then we can re-match to BFE if necessary during instruction selection. llvm-svn: 209462
* R600: Add dag combine for BFEMatt Arsenault2014-05-223-0/+751
| | | | llvm-svn: 209461
* R600: Implement ComputeNumSignBitsForTargetNode for BFEMatt Arsenault2014-05-221-0/+15
| | | | llvm-svn: 209460
* R600: Expand mul24 for GPUs without itMatt Arsenault2014-05-222-3/+10
| | | | llvm-svn: 209458
* R600: Expand mad24 for GPUs without itMatt Arsenault2014-05-222-0/+14
| | | | llvm-svn: 209457
* R600: Add intrinsics for mad24Matt Arsenault2014-05-222-0/+26
| | | | llvm-svn: 209456
* R600/SI: Match fp_to_uint / uint_to_fp for f64Matt Arsenault2014-05-222-0/+18
| | | | llvm-svn: 209388
* R600: Partially fix constant initializers for structs and vectors.Matt Arsenault2014-05-212-0/+55
| | | | | | | This should extend the current workaround to work with structs that only contain legal, scalar types. llvm-svn: 209331
* R600: Add failing testcases for constant initializers.Matt Arsenault2014-05-212-13/+47
| | | | | | | | Constant initializers involving illegal types hit an assertion. Patch by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 209330
* R600/SI: Promote f32 SELECT to i32Tom Stellard2014-05-161-1/+2
| | | | llvm-svn: 209024
* R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0Tom Stellard2014-05-151-0/+25
| | | | llvm-svn: 208886
* R600/SI: Use VALU instructions for i1 opsTom Stellard2014-05-152-12/+36
| | | | llvm-svn: 208885
* Rename ComputeMaskedBits to computeKnownBits. "Masked" has beenJay Foad2014-05-141-1/+1
| | | | | | inappropriate since it lost its Mask parameter in r154011. llvm-svn: 208811
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-0/+9
| | | | | | This was broken by r208479 llvm-svn: 208740
* R600: Add mul24 intrinsicsMatt Arsenault2014-05-122-0/+25
| | | | llvm-svn: 208604
* Make SimplifyDemandedBits understand BUILD_PAIRMatt Arsenault2014-05-121-0/+36
| | | | llvm-svn: 208598
* R600/SI: Fold fabs/fneg into src input modifierVincent Lejeune2014-05-102-0/+22
| | | | llvm-svn: 208480
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-103-3/+5
| | | | llvm-svn: 208479
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-0/+14
| | | | llvm-svn: 208432
* R600/SI: Fix SMRD pattern for offsets > 32 bitsTom Stellard2014-05-091-0/+18
| | | | | | We were dropping the high bits of 64-bit immediate offsets. llvm-svn: 208431
* R600: Expand i64 SELECT_CCTom Stellard2014-05-091-0/+19
| | | | llvm-svn: 208430
* R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine()Tom Stellard2014-05-091-1/+1
| | | | llvm-svn: 208429
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