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* R600/SI: Use i32 vectors for resources and samplersMarek Olsak2014-07-113-86/+86
| | | | | | | | This affects new intrinsics only. What surprises me is that v32i8 still works. llvm-svn: 212831
* R600/SI: add sample and image intrinsics exposing all instruction fieldsMarek Olsak2014-07-113-0/+627
| | | | | | | | | | | We need the intrinsics with offsets, so why not just add them all. The R128 parameter will also be useful for reducing SGPR usage. GL_ARB_image_load_store also adds some image GLSL modifiers like "coherent", so Mesa will probably translate those to slc, glc, etc. When LLVM 3.5 is released, I'll switch Mesa to these new intrinsics. llvm-svn: 212830
* R600: Implement float to long/ulongJan Vesely2014-07-103-49/+386
| | | | | | | | | | | | | | Use alg. from LegalizeDAG.cpp Move Expand setting to SIISellowering v2: Extend existing tests instead of creating new ones v3: use separate LowerFPTOSINT function v4: use TargetLowering::expandFP_TO_SINT add comment about using FP_TO_SINT for uints Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 212773
* Revert "Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), ↵Matt Arsenault2014-07-101-0/+35
| | | | | | | | (trunc b) combine."" Don't try to convert the select condition type. llvm-svn: 212750
* Revert r212640, "Add trunc (select c, a, b) -> select c (trunc a), (trunc b) ↵NAKAMURA Takumi2014-07-101-35/+0
| | | | | | | | combine." This caused miscompilation on, at least, x86-64. SExt(i1 cond) confused other optimizations. llvm-svn: 212708
* R600/SI: Add support for llvm.convert.{to|from}.fp16Matt Arsenault2014-07-102-0/+28
| | | | llvm-svn: 212676
* Add trunc (select c, a, b) -> select c (trunc a), (trunc b) combine.Matt Arsenault2014-07-091-0/+35
| | | | | | Do this if the truncate is free and the select is legal. llvm-svn: 212640
* R600: Fix mishandling of load / store chains.Matt Arsenault2014-07-071-0/+104
| | | | | | | | Fixes various bugs with reordering loads and stores. Scalarized vector loads weren't collecting the chains at all. llvm-svn: 212473
* R600: Promote i64 loads to v2i32Tom Stellard2014-07-023-8/+7
| | | | llvm-svn: 212216
* Revert "Temporary hack to try cleaning extra .s file from bots."Matt Arsenault2014-06-271-1/+0
| | | | llvm-svn: 211967
* Temporary hack to try cleaning extra .s file from bots.Matt Arsenault2014-06-271-0/+1
| | | | llvm-svn: 211963
* Fix test so it doesn't try to write out temporary files into the test tree.David Blaikie2014-06-271-1/+1
| | | | llvm-svn: 211916
* R600: Don't crash on unhandled instruction in promote allocaMatt Arsenault2014-06-273-0/+65
| | | | llvm-svn: 211906
* R600: Add some testcases for promote alloca pass.Matt Arsenault2014-06-271-1/+68
| | | | | | | More complicated GEPs are skipped. Add some tests to actually stress this skipping. llvm-svn: 211859
* R600/SI: Add FP mode bits to binary.Matt Arsenault2014-06-261-0/+10
| | | | | | | | The default rounding mode to initialize the mode register needs to be reported to the runtime. Fill in other bits a kernel may be interested in setting for future use. llvm-svn: 211791
* R600: Fix vector FMAMatt Arsenault2014-06-261-7/+65
| | | | llvm-svn: 211757
* R600: Promote i64 stores to v2i32Tom Stellard2014-06-241-2/+1
| | | | | | Now we need only one 64-bit pattern for stores. llvm-svn: 211643
* R600: Fix inconsistency in rsq instructions.Matt Arsenault2014-06-244-0/+51
| | | | | | | | | | | | | R600 was using a clamped version of rsq, but SI was not. Add a new rsq_clamped intrinsic and use them consistently. It's unclear to me from the documentation what behavior the R600 instructions have, so I assume they have the legacy behavior described by the SI documents. For R600, use RECIPSQRT_IEEE for both llvm.AMDGPU.rsq.legacy and llvm.AMDGPU.rsq. R600 also has RECIPSQRT_FF, which I'm not sure how it fits in here. llvm-svn: 211637
* R600/SI: Fix div_scale intrinsic.Matt Arsenault2014-06-231-11/+36
| | | | | | | The operand that must match one of the others does matter, and implement selecting for it. llvm-svn: 211523
* R600: Move add/sub with overflow out of AMDILISelLoweringMatt Arsenault2014-06-234-2/+246
| | | | | | Add more tests for these. llvm-svn: 211517
* R600/SI: Handle i64 sub.Matt Arsenault2014-06-231-17/+33
| | | | | | We can handle it the same way as add llvm-svn: 211514
* R600: Add udivrem testJan Vesely2014-06-221-0/+358
| | | | | | | | | v2: move < %s to the end of the line space after ; add v4i32 test Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211476
* R600/SI: Add patterns for ctpop inside a branchTom Stellard2014-06-202-0/+61
| | | | llvm-svn: 211378
* R600/SI: Add a pattern for f32 ftruncTom Stellard2014-06-201-91/+100
| | | | llvm-svn: 211377
* R600: Expand vector flog2Tom Stellard2014-06-201-0/+79
| | | | llvm-svn: 211376
* R600: Expand vector fexp2Tom Stellard2014-06-202-20/+99
| | | | llvm-svn: 211375
* R600/SI: Add a VALU pattern for i64 xorTom Stellard2014-06-201-0/+26
| | | | llvm-svn: 211373
* R600: Add a few tests I forgot to add.Matt Arsenault2014-06-193-0/+103
| | | | | | These belong with r210827 llvm-svn: 211253
* R600/SI: Add intrinsics for various math instructions.Matt Arsenault2014-06-199-19/+183
| | | | | | | | These will be used for custom lowering and for library implementations of various math functions, so it's useful to expose these as builtins. llvm-svn: 211247
* R600: Handle fnearbyintMatt Arsenault2014-06-181-0/+57
| | | | | | | | The difference from rint isn't really relevant here, so treat them as equivalent. OpenCL doesn't have nearbyint, so this is sort of pointless other than for completeness. llvm-svn: 211229
* R600/SI: add gather4 and getlod intrinsics (v3)Marek Olsak2014-06-182-0/+552
| | | | | | | | | This contains all the previous patches + getlod support on top of it. It doesn't use SDNodes anymore, so it's quite small. It also adds v16i8 to SReg_128, which is used for the sampler descriptor. Reviewed-by: Tom Stellard llvm-svn: 211228
* R600: Expand vector fceilJan Vesely2014-06-182-85/+216
| | | | | | | | | Move fp64 fceil tests to fceil64.ll v2: rebase Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211194
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+27
| | | | llvm-svn: 211187
* R600/SI: Prettier operand printing for 64-bit ops.Matt Arsenault2014-06-181-4/+3
| | | | | | Copy what is done for 32-bit already so the order is about the same. llvm-svn: 211186
* R600: Implement f64 ftrunc, ffloor and fceil.Matt Arsenault2014-06-183-22/+87
| | | | | | CI has instructions for these, so this fixes them for older hardware. llvm-svn: 211183
* R600: Custom lower f64 frint for pre-CIMatt Arsenault2014-06-181-6/+14
| | | | llvm-svn: 211182
* R600: Implement 64bit SRAJan Vesely2014-06-181-0/+130
| | | | | | | v2: Use capitalized variable name Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211159
* R600: Implement 64bit SRLJan Vesely2014-06-181-0/+126
| | | | | | | v2: use C++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211158
* R600: Implement 64bit SHLJan Vesely2014-06-181-2/+115
| | | | | | | v2: Use c++ style comment Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 211157
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-171-0/+57
| | | | llvm-svn: 211116
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+57
| | | | llvm-svn: 211115
* R600: Use LDS and vectors for private memoryTom Stellard2014-06-178-55/+127
| | | | llvm-svn: 211110
* SelectionDAG: Expand i64 = FP_TO_SINT i32Tom Stellard2014-06-171-0/+12
| | | | llvm-svn: 211108
* R600: Add a rotr testcase I forgot to addMatt Arsenault2014-06-151-0/+58
| | | | llvm-svn: 211002
* R600: Remove a few more things from AMDILISelLoweringMatt Arsenault2014-06-151-0/+50
| | | | | | | Try to keep all the setOperationActions for integer ops together. llvm-svn: 211001
* R600: Fix assert on vector sdivMatt Arsenault2014-06-151-0/+32
| | | | llvm-svn: 211000
* R600: Report that integer division is expensive.Matt Arsenault2014-06-151-4/+54
| | | | | | Divides by weird constants now emit much better code. llvm-svn: 210995
* Don't expect tests always crashing. Add "REQUIRES:asserts".NAKAMURA Takumi2014-06-152-0/+2
| | | | llvm-svn: 210983
* R600: Add failing testcases.Matt Arsenault2014-06-142-0/+28
| | | | | | | These are reduced from assert in the OpenCV CvtColor8u.BGR5652GRAY test. llvm-svn: 210969
* R600: Fix asserts related to constant initializersMatt Arsenault2014-06-141-0/+20
| | | | | | | | | | | This would assert if a constant address space was extern and therefore didn't have an initializer. If the initializer was undef, it would hit the unreachable unhandled initializer case. An extern global should never really occur since we don't have machine linking, but bugpoint likes to remove initializers. llvm-svn: 210967
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