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* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-39/+0
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-0/+39
| | | | llvm-svn: 218254
* R600: Un-xfail a test which passes with pass disabledMatt Arsenault2014-09-191-2/+1
| | | | llvm-svn: 218165
* R600/SI: Un-xfail tests which work nowMatt Arsenault2014-09-193-43/+56
| | | | llvm-svn: 218164
* R600/SI: Un xfail a test that works nowMatt Arsenault2014-09-191-3/+2
| | | | llvm-svn: 218162
* R600/SI: Fix test to prepare for schedulerMatt Arsenault2014-09-191-2/+2
| | | | llvm-svn: 218131
* R600: Better fix for bug 20982Matt Arsenault2014-09-191-4/+3
| | | | | | Just do the left shift as unsigned to avoid the UB. llvm-svn: 218092
* R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault2014-09-181-6/+4
| | | | | | | I'm not sure what the hardware actually does, so don't bother trying to fold it for now. llvm-svn: 218057
* Exclude known and bugzilled failures from UBSan bootstrapAlexey Samsonov2014-09-171-0/+3
| | | | llvm-svn: 217979
* R600/SI: Change formatting of printed FP immediatesMatt Arsenault2014-09-175-11/+181
| | | | | | | | | | Only 1 decimal place should be printed for inline immediates. Other constants should be hex constants. Does not include f64 tests because folding those inline immediates currently does not work. llvm-svn: 217964
* R600/SI: Prefer selecting more e64 instruction forms.Matt Arsenault2014-09-156-9/+81
| | | | | | | | Add some more tests to make sure better operand choices are still made. Leave some cases that seem to have no reason to ever be e64 alone. llvm-svn: 217789
* R600/SI: Make sure double vector fmul is testedMatt Arsenault2014-09-151-4/+29
| | | | llvm-svn: 217787
* R600/SI: Add some mubuf testcases.Matt Arsenault2014-09-151-0/+34
| | | | | | | | | | | | | | | | I noticed some odd looking cases where addr64 wasn't set when storing to a pointer in an SGPR. This seems to be intentional, and partially tested already. The documentation seems to describe addr64 in terms of which registers addressing modifiers come from, but I would expect to always need addr64 when using 64-bit pointers. If no offset is applied, it makes sense to not need to worry about doing a 64-bit add for the final address. A small immediate offset can be applied, so is it OK to not have addr64 set if a carry is necessary when adding the base pointer in the resource to the offset? llvm-svn: 217785
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+182
| | | | llvm-svn: 217777
* R600/SI: Fix broken check linesMatt Arsenault2014-09-141-2/+2
| | | | llvm-svn: 217736
* R600/SI: Fix off by 1 error in used register countMatt Arsenault2014-09-111-1/+8
| | | | | | | The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636
* Add DAG combine for shl + add of constants.Matt Arsenault2014-09-113-7/+94
| | | | | | | | | | | | | | Do (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) This is already done for multiplies, but since multiplies by powers of two are turned into shifts, we also need to handle it here. This might want checks for isLegalAddImmediate to avoid transforming an add of a legal immediate with one that isn't. llvm-svn: 217610
* R600: Test local atomics for evergreenAaron Watry2014-09-111-0/+27
| | | | | | | | Now that the operations are all implemented, we can test this sub-arch here. Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217595
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-0/+26
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600: Custom lower fremMatt Arsenault2014-09-101-0/+103
| | | | llvm-svn: 217553
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-085-4/+509
| | | | llvm-svn: 217379
* R600/SI: Relax a few tests to help enable schedulerMatt Arsenault2014-09-066-25/+25
| | | | llvm-svn: 217320
* R600/SI: Fix broken check lines.Matt Arsenault2014-09-062-6/+7
| | | | | | Fix missing check, and hardcoded register numbers. llvm-svn: 217318
* R600/SI: Use same complex patterns for DS atomicsMatt Arsenault2014-09-052-1/+43
| | | | | | | This fixes hitting the same negative base offset problem that was already fixed for regular loads and stores. llvm-svn: 217256
* R600: Fix FROUNDJan Vesely2014-09-051-6/+8
| | | | | | | | round halfway cases away from zero Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 217250
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-057-8/+8
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-033-16/+134
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Add a pattern for i64 and in a branchTom Stellard2014-09-031-0/+20
| | | | llvm-svn: 217041
* R600/SI: Relax some ordering in tests.Matt Arsenault2014-09-024-26/+31
| | | | | | This will help with enabling misched llvm-svn: 216971
* R600/SI: Fix hardcoded register numbers in testMatt Arsenault2014-09-021-1/+1
| | | | llvm-svn: 216944
* R600/SI: Add failing testcase.Matt Arsenault2014-09-021-0/+43
| | | | | | | This is broken when 64-bit add is only partially moved to the VALU. llvm-svn: 216933
* Fix interference caused by fmul 2, x -> fadd x, xMatt Arsenault2014-09-022-40/+96
| | | | | | | | If an fmul was introduced by lowering, it wouldn't be folded into a multiply by a constant since the earlier combine would have replaced the fmul with the fadd. llvm-svn: 216932
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+173
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-2/+53
| | | | llvm-svn: 216279
* R600/SI: Use a ComplexPattern for DS loads and storesTom Stellard2014-08-225-88/+111
| | | | llvm-svn: 216278
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-211-0/+28
| | | | llvm-svn: 216220
* R600/SI: Make sure SCRATCH_WAVE_OFFSET is added as Live-In to the functionTom Stellard2014-08-211-3/+5
| | | | | | This fixes a crash in an ocl conformance test. llvm-svn: 216219
* R600/SI: Move all fabs / fneg handling to patternsMatt Arsenault2014-08-154-18/+106
| | | | llvm-svn: 215749
* R600/SI: Use source modifiers for f64 fnegMatt Arsenault2014-08-152-0/+148
| | | | llvm-svn: 215748
* R600/SI: Use source modifier for f64 fabsMatt Arsenault2014-08-151-0/+97
| | | | llvm-svn: 215747
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-0/+286
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* R600/SI: Add intrinsic for ldexpMatt Arsenault2014-08-151-0/+22
| | | | llvm-svn: 215734
* R600/SI: Implement isLegalAddressingModeMatt Arsenault2014-08-151-0/+60
| | | | | | | | | | | | | The default assumes that a 16-bit signed offset is used. LDS instruction use a 16-bit unsigned offset, so it wasn't being used in some cases where it was assumed a negative offset could be used. More should be done here, but first isLegalAddressingMode needs to gain an addressing mode argument. For now, copy most of the rest of the default implementation with the immediate offset change. llvm-svn: 215732
* R600: Correctly set the src value offset for scalarized kernel argsMatt Arsenault2014-08-131-0/+18
| | | | | | | | | | This for some reason fixes v1i64 kernel arguments on pre-SI. This currently breaks some other cases in the kernel-args.ll test for R600, but I'm not particularly confident in the new output. VTX_READ_* are not used for some of the scalarized cases, and the code reading from the constant buffer doesn't make much sense to me. llvm-svn: 215564
* Fix classof for ISD::INTRINSIC_W_CHAIN and INTRINSIC_VOIDHal Finkel2014-08-131-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unfortunately, our use of the SDNode class hierarchy for INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes is somewhat broken right now. These nodes sometimes are used for memory intrinsics (those with MachineMemOperands), and sometimes not. When not, the nodes are not created as instances of MemIntrinsicSDNode, but rather created as some other subclass of SDNode using DAG::getNode. When they are memory intrinsics, they are created using DAG::getMemIntrinsicNode as instances of MemIntrinsicSDNode. MemIntrinsicSDNode is a subclass of MemSDNode, but prior to r214452, we had a non-self-consistent setup whereby MemIntrinsicSDNode::classof on INTRINSIC_W_CHAIN and INTRINSIC_VOID would return true but MemSDNode::classof on INTRINSIC_W_CHAIN and INTRINSIC_VOID would return false. In r214452, MemSDNode::classof was changed to return true for INTRINSIC_W_CHAIN and INTRINSIC_VOID, which is now self-consistent. The problem is that neither the pre-r214452 logic and the post-r214452 logic are really right. The truth is that not all INTRINSIC_W_CHAIN and INTRINSIC_VOID nodes are instances of MemIntrinsicSDNode (or MemSDNode for that matter), and the return value from classof needs to reflect that. This was broken before r214452 (because MemIntrinsicSDNode::classof always returned true), and was broken afterward (because MemSDNode::classof also always returned true), and will now be correct. The minimal solution is to grab one of the SubclassData bits (there is one left for MemIntrinsicSDNode nodes) and use it to store whether or not a particular INTRINSIC_W_CHAIN or INTRINSIC_VOID is really an instance of MemIntrinsicSDNode or not. Doing this allows both MemIntrinsicSDNode::classof and MemSDNode::classof to return the correct answer for the underlying object for both the memory-intrinsic and non-memory-intrinsic cases. This fixes the problem that r214452 created in the SelectionDAGDumper (thanks to Matt Arsenault for pointing it out). Because PowerPC does not implement getTgtMemIntrinsic, this change breaks test/CodeGen/PowerPC/unal-altivec-wint.ll. I've XFAILed it for now, and will fix it in a follow-up commit. llvm-svn: 215511
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-121-0/+244
| | | | | | | | | v2: drop enum keyword use correct extension mode don't bother computing the sign in unsinged case Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215462
* R600: Use i24 optimized path for SREMJan Vesely2014-08-121-0/+118
| | | | | | | | | v2: add tests rename LowerSDIV24 to LowerSDIVREM24 handle the rem part in this function Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215460
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-117-22/+37
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add check for low 32 bits of encoding to mubuf testsTom Stellard2014-08-111-7/+7
| | | | | | | | There are no variable values like registers encoded in the low 32 bits of MUBUF instructions, so it is relatively easy to check these bits, and it will help prevent us from introducing encoding bugs. llvm-svn: 215397
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-111-10/+9
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
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