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* R600/SI: Add global atomicrmw xchgAaron Watry2014-10-171-0/+80
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220110
* R600/SI: Add global atomicrmw xorAaron Watry2014-10-171-0/+80
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220109
* R600/SI: Add global atomicrmw orAaron Watry2014-10-171-0/+80
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220108
* R600/SI: Add global atomicrmw min/uminAaron Watry2014-10-171-0/+160
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220107
* R600/SI: Add global atomicrmw max/umaxAaron Watry2014-10-171-0/+160
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220106
* R600/SI: Add global atomicrmw andAaron Watry2014-10-171-0/+80
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220105
* R600/SI: Add global atomicrmw subAaron Watry2014-10-171-0/+80
| | | | | | | | v2: Add separate offset/no-offset tests Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220104
* R600/SI: Fix/add tests for atomicrmw addAaron Watry2014-10-171-3/+45
| | | | | | | | | | | | | The previous tests claimed to test constant offsets in the function name, but the tests weren't actually testing them. Clone the tests, and do testing of all combinations of the following: 1) with/without constant pointer offset 2) 32/64-bit addressing modes 3) Usage and non-usage of the return value from the atomicrmw Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220103
* R600: Rename atomic_load global tests to atomic_addAaron Watry2014-10-171-8/+8
| | | | | | | | The function name now matches what it's actually testing. Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 220102
* R600/SI: Allow commuting with source modifiersMatt Arsenault2014-10-171-0/+50
| | | | llvm-svn: 220066
* R600/SI: Allow comuting fp immediatesMatt Arsenault2014-10-171-9/+31
| | | | llvm-svn: 220062
* R600/SI: Remove SI_BUFFER_RSRC pseudoMatt Arsenault2014-10-171-1/+1
| | | | | | | Just use REG_SEQUENCE directly, so there are fewer instructions to need to deal with later. llvm-svn: 220056
* R600: Add EG to FMA testJan Vesely2014-10-171-1/+14
| | | | | | Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 220045
* SelectionDAG: Add sext_inreg optimizationsJan Vesely2014-10-171-0/+26
| | | | | | | | | | v2: use dyn_cast fixup comments v3: use cast Reviewed-by: Matt Arsenault <arsenm2@gmail.com> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 220044
* R600: Fix nonsensical implementation of computeKnownBits for BFEMatt Arsenault2014-10-161-0/+15
| | | | | | This was resulting in invalid simplifications of sdiv llvm-svn: 219953
* R600/SI: Fix bug where immediates were being used in DS addr operandsTom Stellard2014-10-151-0/+18
| | | | | | | | | | | | | | | | | | | The SelectDS1Addr1Offset complex pattern always tries to store constant lds pointers in the offset operand and store a zero value in the addr operand. Since the addr operand does not accept immediates, the zero value needs to first be copied to a register. This newly created zero value will not go through normal instruction selection, so we need to manually insert a V_MOV_B32_e32 in the complex pattern. This bug was hidden by the fact that if there was another zero value in the DAG that had not been selected yet, then the CSE done by the DAG would use the unselected node for the addr operand rather than the one that was just created. This would lead to the zero value being selected and the DAG automatically inserting a V_MOV_B32_e32 instruction. llvm-svn: 219848
* R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.Matt Arsenault2014-10-152-0/+56
| | | | llvm-svn: 219823
* R600: Fix miscompiles when BFE has multiple usesMatt Arsenault2014-10-151-0/+22
| | | | | | SimplifyDemandedBits would break the other uses of the operand. llvm-svn: 219819
* Reapply "R600: Add new intrinsic to read work dimensions"Jan Vesely2014-10-141-0/+16
| | | | | | | | | This effectively reverts revert 219707. After fixing the test to work with new function name format and renamed intrinsic. Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219710
* Revert "R600: Add new intrinsic to read work dimensions"Rafael Espindola2014-10-141-16/+0
| | | | | | | | This reverts commit r219705. CodeGen/R600/work-item-intrinsics.ll was failing on linux. llvm-svn: 219707
* R600: Add new intrinsic to read work dimensionsJan Vesely2014-10-141-0/+16
| | | | | | | | | | | | | | v2: Add SI lowering Add test v3: Place work dimensions after the kernel arguments. v4: Calculate offset while lowering arguments v5: rebase v6: change prefix to AMDGPU Reviewed-by: Tom Stellard <tom@stellard.net> Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 219705
* R600/SI: Use DS offsets for constant addressesMatt Arsenault2014-10-142-0/+45
| | | | | | | | Use 0 as the base address for a constant address, so if we have a constant address we can save moves and form read2/write2s. llvm-svn: 219698
* llvm/test/CodeGen: Some tests don't REQUIRE asserts any more. Remove them.NAKAMURA Takumi2014-10-124-4/+0
| | | | llvm-svn: 219581
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-1016-209/+213
| | | | | | | Match SC by using offset/offset0/offset1 and printing in decimal. llvm-svn: 219537
* R600/SI: Match read2/write2 stride 64 versionsMatt Arsenault2014-10-105-9/+399
| | | | llvm-svn: 219536
* R600/SI: Add load / store machine optimizer pass.Matt Arsenault2014-10-103-6/+843
| | | | | | | | | | | | | Currently this only functions to match simple cases where ds_read2_* / ds_write2_* instructions can be used. In the future it might match some of the other weird load patterns, such as direct to LDS loads. Currently enabled only with a subtarget feature to enable easier testing. llvm-svn: 219533
* R600/SI: Legalize CopyToReg during instruction selectionTom Stellard2014-10-091-0/+26
| | | | | | | The instruction emitter will crash if it encounters a CopyToReg node with a non-register operand like FrameIndex. llvm-svn: 219428
* R600/SI: Legalize INSERT_SUBREG instructions during PostISelFoldingTom Stellard2014-10-091-0/+15
| | | | | | | | LLVM assumes INSERT_SUBREG will always have register operands, so we need to legalize non-register operands, like FrameIndexes, to avoid random assertion failures. llvm-svn: 219420
* R600/SI: Remove assertion in SIInstrInfo::areLoadsFromSameBasePtr()Tom Stellard2014-10-071-0/+18
| | | | | | | Added a FIXME coment instead, we need to handle the case where the two DS instructions being compared have different numbers of operands. llvm-svn: 219236
* R600/SI: Custom lower f64 -> i64 conversionsMatt Arsenault2014-10-034-34/+122
| | | | llvm-svn: 219038
* R600: Custom lower [s|u]int_to_fp for i64 -> f64Matt Arsenault2014-10-032-3/+67
| | | | llvm-svn: 219037
* R600/SI: Fix ftrunc f64 conformance failures.Matt Arsenault2014-10-034-3/+113
| | | | | | Re-add the tests since they were deleted at some point llvm-svn: 219036
* R600: Align functions to 256 bytesTom Stellard2014-10-031-0/+2
| | | | llvm-svn: 219002
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-01265-1519/+1520
| | | | | | table llvm-svn: 218776
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-305-15/+15
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600: Fix broken check lines, missing scalar case.Matt Arsenault2014-09-301-21/+31
| | | | llvm-svn: 218655
* R600/SI: Also fix fsub + fadd a, a to mad combinesMatt Arsenault2014-09-292-0/+64
| | | | llvm-svn: 218609
* R600/SI: Fix using mad with multiplies by 2Matt Arsenault2014-09-291-6/+152
| | | | | | | | | These turn into fadds, so combine them into the target mad node. fadd (fadd (a, a), b) -> mad 2.0, a, b llvm-svn: 218608
* R600/SI: Add strict check lines to div_scale tests.Matt Arsenault2014-09-261-16/+255
| | | | | | | | | This has weird operand requirements so it's worthwhile to have very strict checks for its operands. Add different combinations of SGPR operands. llvm-svn: 218535
* R600/SI Allow same SGPR to be used for multiple operandsMatt Arsenault2014-09-261-0/+96
| | | | | | | | | | | Instead of moving the first SGPR that is different than the first, legalize the operand that requires the fewest moves if one SGPR is used for multiple operands. This saves extra moves and is also required for some instructions which require that the same operand be used for multiple operands. llvm-svn: 218532
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-265-11/+11
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Don't move operands that are required to be SGPRsMatt Arsenault2014-09-261-9/+33
| | | | | | | | e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. llvm-svn: 218529
* R600/SI: Fix using wrong operand indices when commutingMatt Arsenault2014-09-261-2/+2
| | | | | | | | | | | | | No test since the current SIISelLowering::legalizeOperands effectively hides this, and the general uses seem to only fire on SALU instructions which don't have modifiers between the operands. When trying to use legalizeOperands immediately after instruction selection, it now sees a lot more patterns it did not see before which break on this. llvm-svn: 218527
* R600: Avoid repeated check linesMatt Arsenault2014-09-261-20/+18
| | | | llvm-svn: 218487
* R600/SI: Fix emitting trailing whitespace after s_waitcntMatt Arsenault2014-09-261-4/+4
| | | | llvm-svn: 218486
* R600: Fix some missing conversion testcasesMatt Arsenault2014-09-253-4/+44
| | | | llvm-svn: 218474
* Remove duplicated RUN lines in middle of testMatt Arsenault2014-09-251-2/+0
| | | | llvm-svn: 218473
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-0/+39
| | | | llvm-svn: 218457
* R600/SI: Fix weird CHECK-DAG usageMatt Arsenault2014-09-242-4/+4
| | | | | | This prevents these from failing in a future commit. llvm-svn: 218356
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-246-36/+69
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
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