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* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-113-36/+24
| | | | | | | This saves a second compare and an and / or by using the unordered comparison instructions. llvm-svn: 224066
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-114-16/+6
| | | | llvm-svn: 224065
* MISched: Fix moving stores across barriersTom Stellard2014-12-081-0/+42
| | | | | | | | This fixes an issue with ScheduleDAGInstrs::buildSchedGraph where stores without an underlying object would not be added as a predecessor to the current BarrierChain. llvm-svn: 223717
* R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"Tom Stellard2014-12-061-1/+5
| | | | | | This was changed in r223323. llvm-svn: 223579
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-037-61/+269
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Enable inline assemblyTom Stellard2014-12-031-0/+11
| | | | | | | | We just needed to remove the assertion in AMDGPURegisterInfo::getFrameRegister(), which is called when initializing the parser for inline assembly. llvm-svn: 223197
* R600/SI: Change mubuf offsets to print as decimalMatt Arsenault2014-12-0316-94/+94
| | | | | | This matches SC's behavior. llvm-svn: 223194
* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-022-3/+3
| | | | llvm-svn: 223154
* R600: Cleanup some tests and add missing testcasesMatt Arsenault2014-12-026-234/+363
| | | | llvm-svn: 223151
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-0/+12
| | | | llvm-svn: 223125
* R600/SI: Fix assertion on sign extend of 3 vectorsMatt Arsenault2014-11-281-2/+47
| | | | | | | This was trying to create an MVT with 3x vectors which created an invalid EVT llvm-svn: 222942
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-13/+28
| | | | llvm-svn: 222631
* R600/SI: Add additional tests for i1 loadsMatt Arsenault2014-11-231-1/+22
| | | | llvm-svn: 222629
* R600/SI: Fix broken check lines and modernize prefixesMatt Arsenault2014-11-232-48/+50
| | | | | | Use -LABEL and remove -CHECK llvm-svn: 222628
* R600/SI: Fix missing -verify-machineinstrs on a testMatt Arsenault2014-11-231-1/+1
| | | | llvm-svn: 222627
* R600/SI: Add a failing test case for offset order in ds_read2 instructionsTom Stellard2014-11-211-0/+44
| | | | llvm-svn: 222585
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-1/+2
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-213-28/+57
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* R600/SI: Use hex notation for constant in testTom Stellard2014-11-211-1/+1
| | | | llvm-svn: 222578
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-192-15/+15
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+238
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Move SIFixSGPRCopies to inst selector passesMatt Arsenault2014-11-183-4/+17
| | | | | | | | | | | | This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
* R600/SI: Make sure resource descriptors are always stored in SGPRsTom Stellard2014-11-181-0/+51
| | | | llvm-svn: 222253
* R600: Permute operands when selecting legacy min/maxMatt Arsenault2014-11-153-19/+101
| | | | | | | | | | This gets the correct NaN behavior based on the compare type the hardware uses. This now passes the new piglit test I have for this on SI. Add stricter tests for the operand order. llvm-svn: 222079
* R600/SI: Fix spilling of m0 registerTom Stellard2014-11-141-0/+34
| | | | | | | | | | If we have spilled the value of the m0 register, then we need to restore it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't write to m0. v_readlane_b32 can't write to m0, so llvm-svn: 222036
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-144-0/+228
| | | | llvm-svn: 222032
* R600/SI: Fix verifier error from a branch on IMPLICIT_DEFMatt Arsenault2014-11-142-22/+21
| | | | | | SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
* R600/SI: Match integer min / max instructionsMatt Arsenault2014-11-142-0/+198
| | | | llvm-svn: 222015
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-27/+114
| | | | llvm-svn: 222012
* R600/SI: Fix fmin_legacy / fmax_legacy matching for SIMatt Arsenault2014-11-133-24/+111
| | | | | | select_cc is expanded on SI, so this was never matched. llvm-svn: 221941
* R600/SI: Use s_movk_i32Matt Arsenault2014-11-134-5/+189
| | | | llvm-svn: 221922
* R600: Fix assert on empty functionMatt Arsenault2014-11-131-0/+20
| | | | | | | | If a function is just an unreachable, this would hit a "this is not a MachO target" assertion because of setting HasSubsectionViaSymbols. llvm-svn: 221920
* R600: Error on initializer for LDS.Matt Arsenault2014-11-1315-31/+67
| | | | | | Also give a proper error for other address spaces. llvm-svn: 221917
* R600/SI: Get rid of FCLAMP_SI pseudoMatt Arsenault2014-11-131-0/+38
| | | | | | | It's not necessary. Also use complex patterns to allow src modifier usage. llvm-svn: 221916
* R600/SI: Allow commuting with src2_modifiersMatt Arsenault2014-11-131-0/+25
| | | | llvm-svn: 221911
* R600/SI: Allow commuting some 3 op instructionsMatt Arsenault2014-11-135-21/+179
| | | | | | | | | | | | | e.g. v_mad_f32 a, b, c -> v_mad_f32 b, a, c This simplifies matching v_madmk_f32. This looks somewhat surprising, but it appears to be OK to do this. We can commute src0 and src1 in all of these instructions, and that's all that appears to matter. llvm-svn: 221910
* R600/SI: Fix broken check prefixes in testMatt Arsenault2014-11-081-31/+30
| | | | llvm-svn: 221565
* R600/SI: Add testcase I forgot to commit from months agoMatt Arsenault2014-11-051-0/+11
| | | | llvm-svn: 221384
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-05236-4889/+4889
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This matches the format produced by the AMD proprietary driver. //==================================================================// // Shell script for converting .ll test cases: (Pass the .ll files you want to convert to this script as arguments). //==================================================================// ; This was necessary on my system so that A-Z in sed would match only ; upper case. I'm not sure why. export LC_ALL='C' TEST_FILES="$*" MATCHES=`grep -v Patterns SIInstructions.td | grep -o '"[A-Z0-9_]\+["e]' | grep -o '[A-Z0-9_]\+' | sort -r` for f in $TEST_FILES; do # Check that there are SI tests: grep -q -e 'verde' -e 'bonaire' -e 'SI' -e 'tahiti' $f if [ $? -eq 0 ]; then for match in $MATCHES; do sed -i -e "s/\([ :]$match\)/\L\1/" $f done # Try to get check lines with partial instruction names sed -i 's/\(;[ ]*SI[A-Z\\-]*: \)\([A-Z_0-9]\+\)/\1\L\2/' $f fi done sed -i -e 's/bb0_1/BB0_1/g' ../../../test/CodeGen/R600/infinite-loop.ll sed -i -e 's/SI-NOT: bfe/SI-NOT: {{[^@]}}bfe/g'../../../test/CodeGen/R600/llvm.AMDGPU.bfe.*32.ll ../../../test/CodeGen/R600/sext-in-reg.ll sed -i -e 's/exp_IEEE/EXP_IEEE/g' ../../../test/CodeGen/R600/llvm.exp2.ll sed -i -e 's/numVgprs/NumVgprs/g' ../../../test/CodeGen/R600/register-count-comments.ll sed -i 's/\(; CHECK[-NOT]*: \)\([A-Z_0-9]\+\)/\1\L\2/' ../../../test/CodeGen/R600/select64.ll ../../../test/CodeGen/R600/sgpr-copy.ll //==================================================================// // Shell script for converting .td files (run this last) //==================================================================// export LC_ALL='C' sed -i -e '/Patterns/!s/\("[A-Z0-9_]\+[ "e]\)/\L\1/g' SIInstructions.td sed -i -e 's/"EXP/"exp/g' SIInstrInfo.td llvm-svn: 221350
* R600/SI: Add an extra check line to make test more strictTom Stellard2014-11-051-0/+1
| | | | llvm-svn: 221349
* Reapply: R600: Make sure to inline all internal functionsTom Stellard2014-11-032-1/+25
| | | | | | | | Function calls aren't supported yet. This was reverted due to build breakages, which should be fixed now. llvm-svn: 221173
* Revert "R600: Make sure to inline all internal functions"Reid Kleckner2014-10-312-25/+1
| | | | | | | | | This reverts commit r220996. It introduced layering violations causing link errors in many configurations. llvm-svn: 221020
* R600: Don't promote allocas when one of the users is a ptrtoint instructionTom Stellard2014-10-311-0/+19
| | | | | | | | We need to figure out how to track ptrtoint values all the way until result is converted back to a pointer in order to correctly rewrite the pointer type. llvm-svn: 220997
* R600: Make sure to inline all internal functionsTom Stellard2014-10-312-1/+25
| | | | | | Function calls aren't supported yet. llvm-svn: 220996
* R600/SI: Add another failing testcase for i1 copiesMatt Arsenault2014-10-221-0/+21
| | | | | | It's not handling phis. llvm-svn: 220371
* R600/SI: Add failing testcase reduced from OpenCVMatt Arsenault2014-10-221-0/+22
| | | | | | | This fails the verifier with: "Expected a VCSrc_32 register, but got a VReg_1 register" llvm-svn: 220368
* Add minnum / maxnum codegenMatt Arsenault2014-10-214-0/+530
| | | | llvm-svn: 220342
* R600/SI: Add missing parameter to div_fmas intrinsicMatt Arsenault2014-10-211-6/+6
| | | | llvm-svn: 220338
* R600: Use default GlobalDirectiveMatt Arsenault2014-10-211-0/+14
| | | | | | | The overridden one wasn't inserting a space, so you would end up with .globalfoo llvm-svn: 220329
* R600/SI: Add pattern for bswapMatt Arsenault2014-10-211-1/+65
| | | | llvm-svn: 220304
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