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* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ↵Tom Stellard2014-10-01265-1519/+1520
| | | | | | table llvm-svn: 218776
* R600/SI: Fix printing of clamp and omodMatt Arsenault2014-09-305-15/+15
| | | | | | | | No tests for omod since nothing uses it yet, but this should get rid of the remaining annoying trailing zeros after some instructions. llvm-svn: 218692
* R600: Fix broken check lines, missing scalar case.Matt Arsenault2014-09-301-21/+31
| | | | llvm-svn: 218655
* R600/SI: Also fix fsub + fadd a, a to mad combinesMatt Arsenault2014-09-292-0/+64
| | | | llvm-svn: 218609
* R600/SI: Fix using mad with multiplies by 2Matt Arsenault2014-09-291-6/+152
| | | | | | | | | These turn into fadds, so combine them into the target mad node. fadd (fadd (a, a), b) -> mad 2.0, a, b llvm-svn: 218608
* R600/SI: Add strict check lines to div_scale tests.Matt Arsenault2014-09-261-16/+255
| | | | | | | | | This has weird operand requirements so it's worthwhile to have very strict checks for its operands. Add different combinations of SGPR operands. llvm-svn: 218535
* R600/SI Allow same SGPR to be used for multiple operandsMatt Arsenault2014-09-261-0/+96
| | | | | | | | | | | Instead of moving the first SGPR that is different than the first, legalize the operand that requires the fewest moves if one SGPR is used for multiple operands. This saves extra moves and is also required for some instructions which require that the same operand be used for multiple operands. llvm-svn: 218532
* R600/SI: Partially move operand legalization to post-isel hook.Matt Arsenault2014-09-265-11/+11
| | | | | | | | | Disable the SGPR usage restriction parts of the DAG legalizeOperands. It now should only be doing immediate folding until it can be replaced later. The real legalization work is now done by the other SIInstrInfo::legalizeOperands llvm-svn: 218531
* R600/SI: Don't move operands that are required to be SGPRsMatt Arsenault2014-09-261-9/+33
| | | | | | | | e.g. v_cndmask_b32 requires the condition operand be an SGPR. If one of the source operands were an SGPR, that would be considered the one SGPR use and the condition operand would be illegally moved. llvm-svn: 218529
* R600/SI: Fix using wrong operand indices when commutingMatt Arsenault2014-09-261-2/+2
| | | | | | | | | | | | | No test since the current SIISelLowering::legalizeOperands effectively hides this, and the general uses seem to only fire on SALU instructions which don't have modifiers between the operands. When trying to use legalizeOperands immediately after instruction selection, it now sees a lot more patterns it did not see before which break on this. llvm-svn: 218527
* R600: Avoid repeated check linesMatt Arsenault2014-09-261-20/+18
| | | | llvm-svn: 218487
* R600/SI: Fix emitting trailing whitespace after s_waitcntMatt Arsenault2014-09-261-4/+4
| | | | llvm-svn: 218486
* R600: Fix some missing conversion testcasesMatt Arsenault2014-09-253-4/+44
| | | | llvm-svn: 218474
* Remove duplicated RUN lines in middle of testMatt Arsenault2014-09-251-2/+0
| | | | llvm-svn: 218473
* R600/SI: Add support for global atomic addTom Stellard2014-09-251-0/+39
| | | | llvm-svn: 218457
* R600/SI: Fix weird CHECK-DAG usageMatt Arsenault2014-09-242-4/+4
| | | | | | This prevents these from failing in a future commit. llvm-svn: 218356
* R600/SI: Enable selecting SALU inside branchesTom Stellard2014-09-246-36/+69
| | | | | | We can do this now that the FixSGPRLiveRanges pass is working. llvm-svn: 218353
* Revert "R600/SI: Add support for global atomic add"Tom Stellard2014-09-221-39/+0
| | | | | | | | | This reverts commit r218254. The global_atomics.ll test fails with asserts disabled. For some reason, the compiler fails to produce the atomic no return variants. llvm-svn: 218257
* R600/SI: Add support for global atomic addTom Stellard2014-09-221-0/+39
| | | | llvm-svn: 218254
* R600: Un-xfail a test which passes with pass disabledMatt Arsenault2014-09-191-2/+1
| | | | llvm-svn: 218165
* R600/SI: Un-xfail tests which work nowMatt Arsenault2014-09-193-43/+56
| | | | llvm-svn: 218164
* R600/SI: Un xfail a test that works nowMatt Arsenault2014-09-191-3/+2
| | | | llvm-svn: 218162
* R600/SI: Fix test to prepare for schedulerMatt Arsenault2014-09-191-2/+2
| | | | llvm-svn: 218131
* R600: Better fix for bug 20982Matt Arsenault2014-09-191-4/+3
| | | | | | Just do the left shift as unsigned to avoid the UB. llvm-svn: 218092
* R600: Bug 20982 - Avoid undefined left shift of negative valueMatt Arsenault2014-09-181-6/+4
| | | | | | | I'm not sure what the hardware actually does, so don't bother trying to fold it for now. llvm-svn: 218057
* Exclude known and bugzilled failures from UBSan bootstrapAlexey Samsonov2014-09-171-0/+3
| | | | llvm-svn: 217979
* R600/SI: Change formatting of printed FP immediatesMatt Arsenault2014-09-175-11/+181
| | | | | | | | | | Only 1 decimal place should be printed for inline immediates. Other constants should be hex constants. Does not include f64 tests because folding those inline immediates currently does not work. llvm-svn: 217964
* R600/SI: Prefer selecting more e64 instruction forms.Matt Arsenault2014-09-156-9/+81
| | | | | | | | Add some more tests to make sure better operand choices are still made. Leave some cases that seem to have no reason to ever be e64 alone. llvm-svn: 217789
* R600/SI: Make sure double vector fmul is testedMatt Arsenault2014-09-151-4/+29
| | | | llvm-svn: 217787
* R600/SI: Add some mubuf testcases.Matt Arsenault2014-09-151-0/+34
| | | | | | | | | | | | | | | | I noticed some odd looking cases where addr64 wasn't set when storing to a pointer in an SGPR. This seems to be intentional, and partially tested already. The documentation seems to describe addr64 in terms of which registers addressing modifiers come from, but I would expect to always need addr64 when using 64-bit pointers. If no offset is applied, it makes sense to not need to worry about doing a 64-bit add for the final address. A small immediate offset can be applied, so is it OK to not have addr64 set if a carry is necessary when adding the base pointer in the resource to the offset? llvm-svn: 217785
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+182
| | | | llvm-svn: 217777
* R600/SI: Fix broken check linesMatt Arsenault2014-09-141-2/+2
| | | | llvm-svn: 217736
* R600/SI: Fix off by 1 error in used register countMatt Arsenault2014-09-111-1/+8
| | | | | | | The register numbers start at 0, so if only 1 register was used, this was reported as 0. llvm-svn: 217636
* Add DAG combine for shl + add of constants.Matt Arsenault2014-09-113-7/+94
| | | | | | | | | | | | | | Do (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) This is already done for multiplies, but since multiplies by powers of two are turned into shifts, we also need to handle it here. This might want checks for isLegalAddImmediate to avoid transforming an add of a legal immediate with one that isn't. llvm-svn: 217610
* R600: Test local atomics for evergreenAaron Watry2014-09-111-0/+27
| | | | | | | | Now that the operations are all implemented, we can test this sub-arch here. Signed-off-by: Aaron Watry <awatry@gmail.com> Reviewed-by: Matt Arsenault <matthew.arsenault@amd.com> llvm-svn: 217595
* R600/SI: Fix losing chain when fixing reg class of loads.Matt Arsenault2014-09-101-0/+26
| | | | | | | The lost chain resulting in earlier side effecting nodes being deleted. llvm-svn: 217561
* R600: Custom lower fremMatt Arsenault2014-09-101-0/+103
| | | | llvm-svn: 217553
* R600/SI: Replace LDS atomics with no return versionsMatt Arsenault2014-09-085-4/+509
| | | | llvm-svn: 217379
* R600/SI: Relax a few tests to help enable schedulerMatt Arsenault2014-09-066-25/+25
| | | | llvm-svn: 217320
* R600/SI: Fix broken check lines.Matt Arsenault2014-09-062-6/+7
| | | | | | Fix missing check, and hardcoded register numbers. llvm-svn: 217318
* R600/SI: Use same complex patterns for DS atomicsMatt Arsenault2014-09-052-1/+43
| | | | | | | This fixes hitting the same negative base offset problem that was already fixed for regular loads and stores. llvm-svn: 217256
* R600: Fix FROUNDJan Vesely2014-09-051-6/+8
| | | | | | | | round halfway cases away from zero Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 217250
* R600/SI: Use S_ADD_U32 and S_SUB_U32 for low half of 64-bit operationsTom Stellard2014-09-057-8/+8
| | | | | | https://bugs.freedesktop.org/show_bug.cgi?id=83416 llvm-svn: 217248
* R600/SI: Try to keep i32 mul on SALUMatt Arsenault2014-09-033-16/+134
| | | | | | | Also fix bug this exposed where when legalizing an immediate operand, a v_mov_b32 would be created with a VSrc dest register. llvm-svn: 217108
* R600/SI: Add a pattern for i64 and in a branchTom Stellard2014-09-031-0/+20
| | | | llvm-svn: 217041
* R600/SI: Relax some ordering in tests.Matt Arsenault2014-09-024-26/+31
| | | | | | This will help with enabling misched llvm-svn: 216971
* R600/SI: Fix hardcoded register numbers in testMatt Arsenault2014-09-021-1/+1
| | | | llvm-svn: 216944
* R600/SI: Add failing testcase.Matt Arsenault2014-09-021-0/+43
| | | | | | | This is broken when 64-bit add is only partially moved to the VALU. llvm-svn: 216933
* Fix interference caused by fmul 2, x -> fadd x, xMatt Arsenault2014-09-022-40/+96
| | | | | | | | If an fmul was introduced by lowering, it wouldn't be folded into a multiply by a constant since the earlier combine would have replaced the fmul with the fadd. llvm-svn: 216932
* R600/SI: Use mad for fsub + fmulMatt Arsenault2014-08-291-0/+173
| | | | | | | We can use a negate source modifier to match this for fsub. llvm-svn: 216735
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