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* R600/SI: Use RegisterOperands to specify which operands can accept immediatesTom Stellard2015-01-125-18/+18
| | | | | | | | | | | | There are some operands which can take either immediates or registers and we were previously using different register class to distinguish between operands that could take immediates and those that could not. This patch switches to using RegisterOperands which should simplify the backend by reducing the number of register classes and also make it easier to implement the assembler. llvm-svn: 225662
* R600/SI: Remove SIISelLowering::legalizeOperands()Tom Stellard2015-01-0810-12/+33
| | | | | | | | | Its functionality has been replaced by calling SIInstrInfo::legalizeOperands() from SIISelLowering::AdjstInstrPostInstrSelection() and running the SIFoldOperands and SIShrinkInstructions passes. llvm-svn: 225445
* RegisterCoalescer: Fix valuesIdentical() in some subrange merge cases.Matthias Braun2015-01-071-0/+45
| | | | | | | | | | | | | I got confused and assumed SrcIdx/DstIdx of the CoalescerPair is a subregister index in SrcReg/DstReg, but they are actually subregister indices of the coalesced register that get you back to SrcReg/DstReg when applied. Fixed the bug, improved comments and simplified code accordingly. Testcase by Tom Stellard! llvm-svn: 225415
* R600/SI: Commute instructions to enable more folding opportunitiesTom Stellard2015-01-073-4/+4
| | | | llvm-svn: 225410
* R600/SI: Only fold immediates that have one useTom Stellard2015-01-071-0/+35
| | | | | | | Folding the same immediate into multiple instruction will increase program size, which can hurt performance. llvm-svn: 225405
* R600/SI: Add a V_MOV_B64 pseudo instructionTom Stellard2015-01-073-30/+19
| | | | | | | This is used to simplify the SIFoldOperands pass and make it easier to fold immediates. llvm-svn: 225373
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-073-8/+25
| | | | | | | | | | | | | | | This allows folding of sequences like: s[0:1] = s_mov_b64 4 v_add_i32 v0, s0, v0 v_addc_u32 v1, s1, v1 into v_add_i32 v0, 4, v0 v_add_i32 v1, 0, v1 llvm-svn: 225369
* R600/SI: Add combine for isinfinite patternMatt Arsenault2015-01-061-0/+85
| | | | llvm-svn: 225310
* R600/SI: Pattern match isinf to v_cmp_class instructionsMatt Arsenault2015-01-061-0/+45
| | | | llvm-svn: 225307
* R600/SI: Add basic DAG combines for fp_classMatt Arsenault2015-01-061-0/+162
| | | | llvm-svn: 225306
* R600/SI: Add class intrinsicMatt Arsenault2015-01-061-0/+335
| | | | llvm-svn: 225305
* R600/SI: Insert s_waitcnt before s_barrier instructions.Tom Stellard2015-01-062-0/+5
| | | | | | | This ensures that all memory operations are complete when all threads reach the barrier. llvm-svn: 225290
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-06277-308/+308
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* Enable (sext x) == C --> x == (trunc C) combineMatt Arsenault2014-12-212-7/+394
| | | | | | | | | Extend the existing code which handles this for zext. This makes this more useful for targets with ZeroOrNegativeOne BooleanContent and obsoletes a custom combine SI uses for i1 setcc (sext(i1), 0, setne) since the constant will now be shrunk to i1. llvm-svn: 224691
* R600/SI: Only form min/max with 1 use.Matt Arsenault2014-12-193-0/+69
| | | | | | | If the condition is used for something else, this increases the number of instructions. llvm-svn: 224646
* R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operandTom Stellard2014-12-191-0/+39
| | | | | | | | mubuf instructions now define the soffset field using the SCSrc_32 register class which indicates that only SGPRs and inline constants are allowed. llvm-svn: 224622
* R600/SI: Fix f64 inline immediatesMatt Arsenault2014-12-171-0/+272
| | | | llvm-svn: 224458
* IR: Make metadata typeless in assemblyDuncan P. N. Exon Smith2014-12-1515-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that `Metadata` is typeless, reflect that in the assembly. These are the matching assembly changes for the metadata/value split in r223802. - Only use the `metadata` type when referencing metadata from a call intrinsic -- i.e., only when it's used as a `Value`. - Stop pretending that `ValueAsMetadata` is wrapped in an `MDNode` when referencing it from call intrinsics. So, assembly like this: define @foo(i32 %v) { call void @llvm.foo(metadata !{i32 %v}, metadata !0) call void @llvm.foo(metadata !{i32 7}, metadata !0) call void @llvm.foo(metadata !1, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{metadata !3}, metadata !0) ret void, !bar !2 } !0 = metadata !{metadata !2} !1 = metadata !{i32* @global} !2 = metadata !{metadata !3} !3 = metadata !{} turns into this: define @foo(i32 %v) { call void @llvm.foo(metadata i32 %v, metadata !0) call void @llvm.foo(metadata i32 7, metadata !0) call void @llvm.foo(metadata i32* @global, metadata !0) call void @llvm.foo(metadata !3, metadata !0) call void @llvm.foo(metadata !{!3}, metadata !0) ret void, !bar !2 } !0 = !{!2} !1 = !{i32* @global} !2 = !{!3} !3 = !{} I wrote an upgrade script that handled almost all of the tests in llvm and many of the tests in cfe (even handling many `CHECK` lines). I've attached it (or will attach it in a moment if you're speedy) to PR21532 to help everyone update their out-of-tree testcases. This is part of PR21532. llvm-svn: 224257
* R600: Fix min/max matching problems with unordered comparesMatt Arsenault2014-12-124-4/+148
| | | | | | | | The returned operand needs to be permuted for the unordered compares. Also fix incorrectly producing fmin_legacy / fmax_legacy for f64, which don't exist. llvm-svn: 224094
* R600/SI: Don't promote f32 select to i32Matt Arsenault2014-12-124-4/+4
| | | | | | | | This is nice for the instruction patterns, but it complicates min / max matching. The select doesn't have the correct type and would require looking through the bitcasts for the real float operands. llvm-svn: 224092
* Add target hook for whether it is profitable to reduce load widthsMatt Arsenault2014-12-122-15/+213
| | | | | | | | Add an option to disable optimization to shrink truncated larger type loads to smaller type loads. On SI this prevents using scalar load instructions in some cases, since there are no scalar extloads. llvm-svn: 224084
* R600/SI: Use unordered equal instructionsMatt Arsenault2014-12-113-10/+5
| | | | llvm-svn: 224067
* R600/SI: Make more unordered comparisons legalMatt Arsenault2014-12-113-36/+24
| | | | | | | This saves a second compare and an and / or by using the unordered comparison instructions. llvm-svn: 224066
* R600/SI: Use unordered not equal instructionsMatt Arsenault2014-12-114-16/+6
| | | | llvm-svn: 224065
* MISched: Fix moving stores across barriersTom Stellard2014-12-081-0/+42
| | | | | | | | This fixes an issue with ScheduleDAGInstrs::buildSchedGraph where stores without an underlying object would not be added as a predecessor to the current BarrierChain. llvm-svn: 223717
* R600/SI: Restore PrivateGlobalPrefix to the default ELF value of ".L"Tom Stellard2014-12-061-1/+5
| | | | | | This was changed in r223323. llvm-svn: 223579
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-037-61/+269
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Enable inline assemblyTom Stellard2014-12-031-0/+11
| | | | | | | | We just needed to remove the assertion in AMDGPURegisterInfo::getFrameRegister(), which is called when initializing the parser for inline assembly. llvm-svn: 223197
* R600/SI: Change mubuf offsets to print as decimalMatt Arsenault2014-12-0316-94/+94
| | | | | | This matches SC's behavior. llvm-svn: 223194
* R600/SI: Move more information into SIProgramInfo structTom Stellard2014-12-022-3/+3
| | | | llvm-svn: 223154
* R600: Cleanup some tests and add missing testcasesMatt Arsenault2014-12-026-234/+363
| | | | llvm-svn: 223151
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-0/+12
| | | | llvm-svn: 223125
* R600/SI: Fix assertion on sign extend of 3 vectorsMatt Arsenault2014-11-281-2/+47
| | | | | | | This was trying to create an MVT with 3x vectors which created an invalid EVT llvm-svn: 222942
* R600: Fix extloads of i1 on R600/EvergreenMatt Arsenault2014-11-231-13/+28
| | | | llvm-svn: 222631
* R600/SI: Add additional tests for i1 loadsMatt Arsenault2014-11-231-1/+22
| | | | llvm-svn: 222629
* R600/SI: Fix broken check lines and modernize prefixesMatt Arsenault2014-11-232-48/+50
| | | | | | Use -LABEL and remove -CHECK llvm-svn: 222628
* R600/SI: Fix missing -verify-machineinstrs on a testMatt Arsenault2014-11-231-1/+1
| | | | llvm-svn: 222627
* R600/SI: Add a failing test case for offset order in ds_read2 instructionsTom Stellard2014-11-211-0/+44
| | | | llvm-svn: 222585
* R600/SI: Emit s_mov_b32 m0, -1 before every DS instructionTom Stellard2014-11-211-1/+2
| | | | | | | | | | | | This s_mov_b32 will write to a virtual register from the M0Reg class and all the ds instructions now take an extra M0Reg explicit argument. This change is necessary to prevent issues with the scheduler mixing together instructions that expect different values in the m0 registers. llvm-svn: 222583
* R600/SI: Add SIFoldOperands passTom Stellard2014-11-213-28/+57
| | | | | | | This pass attempts to fold the source operands of mov and copy instructions into their uses. llvm-svn: 222581
* R600/SI: Use hex notation for constant in testTom Stellard2014-11-211-1/+1
| | | | llvm-svn: 222578
* R600/SI: Make SIInstrInfo::isOperandLegal() more strictTom Stellard2014-11-192-15/+15
| | | | | | | | | | | | A register operand that has a common sub-class with its instruction's defined register class is not always legal. For example, SReg_32 and M0Reg both have a common sub-class, but we can't use an SReg_32 in instructions that expect a M0Reg. This prevents the llvm.SI.sendmsg.ll test from failing when the fold operand pass is added. llvm-svn: 222368
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+238
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Move SIFixSGPRCopies to inst selector passesMatt Arsenault2014-11-183-4/+17
| | | | | | | | | | | | This should expose more of the actually used VALU instructions to the machine optimization passes. This also should help getting i1 handling into a better state. For not entirly understood reasons, this fixes the split-scalar-i64-add.ll test where a 64-bit add would only partially be moved to the VALU resulting in use of undefined VCC. llvm-svn: 222256
* R600/SI: Make sure resource descriptors are always stored in SGPRsTom Stellard2014-11-181-0/+51
| | | | llvm-svn: 222253
* R600: Permute operands when selecting legacy min/maxMatt Arsenault2014-11-153-19/+101
| | | | | | | | | | This gets the correct NaN behavior based on the compare type the hardware uses. This now passes the new piglit test I have for this on SI. Add stricter tests for the operand order. llvm-svn: 222079
* R600/SI: Fix spilling of m0 registerTom Stellard2014-11-141-0/+34
| | | | | | | | | | If we have spilled the value of the m0 register, then we need to restore it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't write to m0. v_readlane_b32 can't write to m0, so llvm-svn: 222036
* R600/SI: Combine min3/max3 instructionsMatt Arsenault2014-11-144-0/+228
| | | | llvm-svn: 222032
* R600/SI: Fix verifier error from a branch on IMPLICIT_DEFMatt Arsenault2014-11-142-22/+21
| | | | | | SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
* R600/SI: Match integer min / max instructionsMatt Arsenault2014-11-142-0/+198
| | | | llvm-svn: 222015
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