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path: root/llvm/test/CodeGen/R600/work-item-intrinsics.ll
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* R600 -> AMDGPU renameTom Stellard2015-06-131-238/+0
* R600/SI: Enable a lot of existing tests for VI (squashed commits)Marek Olsak2015-02-111-31/+41
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-1/+1
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-39/+39
* Reapply "R600: Add new intrinsic to read work dimensions"Jan Vesely2014-10-141-0/+16
* Revert "R600: Add new intrinsic to read work dimensions"Rafael Espindola2014-10-141-16/+0
* R600: Add new intrinsic to read work dimensionsJan Vesely2014-10-141-0/+16
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ...Tom Stellard2014-10-011-15/+15
* R600: Modernize work item intrinsics testJan Vesely2014-07-311-81/+82
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-5/+5
* R600/SI: Print more immediates in hex formatMatt Arsenault2014-04-151-8/+8
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-121-26/+26
* R600/SI: Use -verify-machineinstrs for most testsTom Stellard2013-10-101-1/+1
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-041-9/+9
* R600: Change the RAT instruction assembly names so they match the docsTom Stellard2013-08-161-9/+9
* Revert "R600: Non vector only instruction can be scheduled on trans unit"Tom Stellard2013-07-311-9/+9
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-07-311-9/+9
* R600: Use KCache for kernel argumentsTom Stellard2013-07-231-9/+9
* R600/SI: Add support for work item and work group intrinsicsTom Stellard2013-06-031-0/+211
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