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path: root/llvm/test/CodeGen/R600/unaligned-load-store.ll
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* R600 -> AMDGPU renameTom Stellard2015-06-131-254/+0
* R600/SI: Don't print offset0/offset1 DS operands when they are 0Tom Stellard2015-04-081-2/+2
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-12/+12
* [opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie2015-02-271-4/+4
* R600/SI: Expand misaligned 16-bit memory accessesTom Stellard2015-02-041-0/+24
* R600/SI: Make more store operations legalTom Stellard2015-02-041-11/+46
* R600: Don't promote i64 stores to v2i32 during DAG legalizationTom Stellard2015-02-041-2/+4
* R600/SI: 64-bit and larger memory access must be at least 4-byte alignedTom Stellard2015-02-021-4/+75
* R600/SI: Merge two test filesTom Stellard2015-02-021-6/+15
* R600/SI: Enable all tests that pass on VI without changesMarek Olsak2015-01-271-0/+1
* Implement new way of expanding extloads.Matt Arsenault2015-01-141-11/+22
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-061-1/+1
* R600/SI: Change all instruction assembly names to lowercase.Tom Stellard2014-11-051-29/+29
* R600/SI: Change how DS offsets are printedMatt Arsenault2014-10-101-6/+6
* R600: Call EmitFunctionHeader() in the AsmPrinter to populate the ELF symbol ...Tom Stellard2014-10-011-8/+8
* R600/SI: Fix broken check linesMatt Arsenault2014-09-141-2/+2
* R600/SI: Use READ2/WRITE2 instructions for 64-bit mem ops with 32-bit alignmentTom Stellard2014-08-221-2/+53
* Add alignment value to allowsUnalignedMemoryAccessMatt Arsenault2014-07-271-0/+17
* R600/SI: Fix broken test.Matt Arsenault2014-07-261-2/+18
* R600/SI: Custom lower SI_IF and SI_ELSE to avoid machine verifier errorsTom Stellard2014-04-291-1/+1
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-131-4/+2
* R600/SI: Change formatting of printed registers.Matt Arsenault2013-11-121-4/+4
* Fix CodeGen for unaligned loads with address spacesMatt Arsenault2013-10-301-0/+19
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