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path: root/llvm/test/CodeGen/PowerPC/variable_elem_vec_extracts.ll
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* [SelectionDAG] Reverse the order of operands in the ISD::ADD created by Targe...Craig Topper2017-12-221-3/+3
* [PPC] Also disable the pre-emit version of reg+reg to reg+imm transformation.Benjamin Kramer2017-12-181-1/+1
* [PowerPC] Convert r+r instructions to r+i (pre and post RA)Nemanja Ivanovic2017-12-151-3/+3
* DAG: Avoid OOB when legalizing vector indexingMatt Arsenault2017-01-101-3/+3
* Adding -verify-machineinstrs option to PowerPC testsEhsan Amiri2016-08-031-3/+3
* Bitcasts between FP and INT values using direct movesNemanja Ivanovic2015-12-101-0/+114
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