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* [mips][FastISel] Implement srem/urem and sdiv/udiv instructions.Vasileios Kalintiris2015-06-012-0/+111
| | | | | | | | | | | | | | | | | | | Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
* [mips][FastISel] Implement the select statement for MIPS FastISel.Vasileios Kalintiris2015-06-011-0/+91
| | | | | | | | | | | | | | | | | | Summary: Implement the LLVM IR select statement for MIPS FastISelsel. Based on a patch by Reed Kotler. Test Plan: "Make check" test included now. Passes test-suite at O2/O0 mips32 r1/r2. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6774 llvm-svn: 238756
* [mips][FastISel] Clobber HI0/LO0 registers in MUL instructions.Vasileios Kalintiris2015-06-011-0/+18
| | | | | | | | | | | | | | | | | | | | | Summary: The contents of the HI/LO registers are unpredictable after the execution of the MUL instruction. In addition to implicitly defining these registers in the MUL instruction definition, we have to mark those registers as dead too. Without this the fast register allocator is running out of registers when the MUL instruction is followed by another one that tries to allocate the AC0 register. Based on a patch by Reed Kotler. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D9825 llvm-svn: 238755
* Revert r238427 - [mips] Make TTypeEncoding indirect to allow .eh_frame to be ↵Daniel Sanders2015-05-281-19/+7
| | | | | | | | read-only. It caused a smaller number of failures than the previous attempt at committing but still caused a couple on the llvm-linux-mips builder. Reverting while I investigate the remainder. llvm-svn: 238483
* [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.Daniel Sanders2015-05-281-7/+19
| | | | | | | | | | | | | | | | | | Summary: Following on from r209907 which made personality encodings indirect, do the same for TType encodings. This fixes the case where a try/catch block needs to generate references to, for example, std::exception in the .gcc_except_table. Reviewers: petarj Reviewed By: petarj Subscribers: srhines, joerg, tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9669 llvm-svn: 238427
* Revert r238190 and r238197: [mips] Make TTypeEncoding indirect to allow ↵Daniel Sanders2015-05-271-23/+7
| | | | | | | | | | .eh_frame to be read-only. This broke the llvm-mips-linux builder and several of our out-of-tree builders. Initial investigations show that the commit probably isn't the problem but reverting anyway while I investigate. llvm-svn: 238302
* [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only.Daniel Sanders2015-05-261-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Following on from r209907 which made personality encodings indirect, do the same for TType encodings. This fixes the case where a try/catch block needs to generate references to, for example, std::exception in the .gcc_except_table. This commit uses DW_EH_PE_sdata8 for N64 as far as is possible at the moment. However, it is possible to end up with DW_EH_PE_sdata4 when a TargetMachine is not available. There's no risk of issues with inconsistency here since the tables are self describing but it does mean there is a small chance of the PC-relative offset being out of range for particularly large programs. Reviewers: petarj Reviewed By: petarj Subscribers: srhines, joerg, tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9669 llvm-svn: 238190
* Revert r237789 - [mips] The naming convention for private labels is ABI ↵Daniel Sanders2015-05-2013-201/+190
| | | | | | | | | dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
* [mips] Fix ehframe-indirect.ll test.Daniel Sanders2015-05-201-20/+25
| | | | | | | | | | | | | | | | | | Summary: -check-prefix replaces the default CHECK prefix rather than adding to it and must be explicitly re-added. Also added the N32 cases. Reviewers: petarj Reviewed By: petarj Subscribers: tberghammer, llvm-commits Differential Revision: http://reviews.llvm.org/D9668 llvm-svn: 237790
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-2013-190/+201
| | | | | | | | | | | | | | | | | Summary: For N32/N64, private labels begin with '.L' but for O32 they begin with '$'. MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: jfb, sandeep, llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D9821 llvm-svn: 237789
* [mips] Correct and improve special-case shuffle instructions.Daniel Sanders2015-05-191-134/+780
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The documentation writes vectors highest-index first whereas LLVM-IR writes them lowest-index first. As a result, instructions defined in terms of left_half() and right_half() had the halves reversed. In addition to correcting them, they have been improved to allow shuffles that use the same operand twice or in reverse order. For example, ilvev used to accept masks of the form: <0, n, 2, n+2, 4, n+4, ...> but now accepts: <0, 0, 2, 2, 4, 4, ...> <n, n, n+2, n+2, n+4, n+4, ...> <0, n, 2, n+2, 4, n+4, ...> <n, 0, n+2, 2, n+4, 4, ...> One further improvement is that splati.[bhwd] is now the preferred instruction for splat-like operations. The other special shuffles are no longer used for splats. This lead to the discovery that <0, 0, ...> would not cause splati.[hwd] to be selected and this has also been fixed. This fixes the enc-3des test from the test-suite on Mips64r6 with MSA. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9660 llvm-svn: 237689
* [mips] Do not place users of $ra in the delay slot of call instructions.Vasileios Kalintiris2015-05-141-0/+183
| | | | | | | | | | | | | | | Summary: When we are trying to fill the delay slot of a call instruction, we must avoid filler instructions that use the $ra register. This fixes the test MultiSource/Applications/JM/lencod when we enable the forward delay slot filler. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9670 llvm-svn: 237362
* [Mips] Return false for isFPCloseToIncomingSP()Petar Jovanovic2015-05-121-0/+32
| | | | | | | | | | | | | On Mips, frame pointer points to the same side of the frame as the stack pointer. This function is used to decide where to put register scavenging spill slot. So far, it was put on the wrong side of the frame, and thus it was too far away from $fp when frame was larger than 2^15 bytes. Patch by Vladimir Radosavljevic. http://reviews.llvm.org/D8895 llvm-svn: 237153
* [mips][FastISel] Handle calls with non legal types i8 and i16.Vasileios Kalintiris2015-05-121-0/+184
| | | | | | | | | | | | | | | | | | Summary: Allow calls with non legal integer types based on i8 and i16 to be processed by mips fast-isel. Based on a patch by Reed Kotler. Test Plan: "Make check" test forthcoming. Test-suite passes at O0/O2 and with mips32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6770 llvm-svn: 237121
* [mips][FastISel] Simplify callabi.ll by using multiple check prefixes.Vasileios Kalintiris2015-05-121-397/+274
| | | | | | | | | | Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9635 llvm-svn: 237119
* [mips][FastISel] Allow computation of addresses from constant expressions.Vasileios Kalintiris2015-05-121-0/+18
| | | | | | | | | | | | | | | | | | | Summary: Try to compute addresses when the offset from a memory location is a constant expression. Based on a patch by Reed Kotler. Test Plan: Passes test-suite for -O0/O2 and mips 32 r1/r2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6767 llvm-svn: 237117
* [mips] Emit the .insn directive for empty basic blocks.Vasileios Kalintiris2015-05-081-0/+27
| | | | | | | | | | | | | | | | | | | Summary: In microMIPS, labels need to know whether they are on code or data. This is indicated with STO_MIPS_MICROMIPS and can be inferred by being followed by instructions. For empty basic blocks, we can ensure this by emitting the .insn directive after the label. Also, this fixes some failures in our out-of-tree microMIPS buildbots, for the exception handling regression tests under: SingleSource/Regression/C++/EH Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9530 llvm-svn: 236815
* Now that we have a soft-float attribute, use it instead of theEric Christopher2015-05-0827-60/+60
| | | | | | hard coded command line option for the Mips soft float tests. llvm-svn: 236801
* [mips] Generate code for insert/extract operations when using the N64 ABI ↵Daniel Sanders2015-05-052-1/+7
| | | | | | | | | | | | | | | | | | | | | | and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
* [mips][msa] Test basic operations for the N32 ABI too.Daniel Sanders2015-05-052-115/+247
| | | | | | | | | | | | | | | | | Summary: This required adding instruction aliases for dneg. N64 will be enabled shortly but requires additional bugfixes. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9341 llvm-svn: 236489
* [mips][msa] Rename main check prefix to 'ALL' in basic operations tests. NFCDaniel Sanders2015-04-302-393/+393
| | | | | | | | | | | | | | | | Summary: The majority of the checks are subtarget independent. The few that aren't will be corrected shortly. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9340 llvm-svn: 236220
* [mips][msa] Use CHECK-LABEL where missing, and remove checks matching the ↵Daniel Sanders2015-04-302-53/+5
| | | | | | | | | | | | | | | | .size directive. NFC. Summary: Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9339 llvm-svn: 236219
* [mips] Add missing signext attributes to MSA basic operations tests. NFC.Daniel Sanders2015-04-301-28/+20
| | | | | | | | | | | | | | | | | Summary: This doesn't make much difference to MIPS32, but it will simplify a MIPS64r6 bugfix which will follow shortly by removing unnecessary sign-extension of parameters. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9338 llvm-svn: 236216
* Mips fast-isel - handle functions which return i8 or i6 .Vasileios Kalintiris2015-04-291-0/+28
| | | | | | | | | | | | | | | | Summary: Allow Mips fast-isel to handle functions which return i8/i16 signed/unsigned. Test Plan: Make check tests are forthcoming. Already passes test-suite at O0/O2 for Mips 32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6765 llvm-svn: 236103
* [mips] Correct 128-bit shifts on 64-bit targets.Daniel Sanders2015-04-293-12/+12
| | | | | | | | | | | | | | | | Summary: The existing code was correct for 32-bit GPR's but not 64-bit GPR's. It now accounts for both cases. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits, mohit.bhakkad, sagar Differential Revision: http://reviews.llvm.org/D9337 llvm-svn: 236099
* Reapply "[mips][FastISel] Implement shift ops for Mips fast-isel.""Vasileios Kalintiris2015-04-271-0/+122
| | | | | | | | This reapplies r235194, which was reverted in r235495 because it was causing a failure in our out-of-tree buildbots for MIPS. With the sign-extension patch in r235718, this patch doesn't cause any problem any more. llvm-svn: 235878
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-04-241-1/+1
| | | | | | | | | | the invoke instruction Same as r235145 for the call instruction - the justification, tradeoffs, etc are all the same. The conversion script worked the same without any false negatives (after replacing 'call' with 'invoke'). llvm-svn: 235755
* Fix correctness check for test_vec_fpextend_doublePirama Arumuga Nainar2015-04-221-7/+9
| | | | | | | | | | | | | | | | Summary: Remove the CHECK-DAG calls introduced in r235341, and add a comment that this test may break due to scheduling variations. This patch completes the fix discussed in http://reviews.llvm.org/D8804 Reviewers: dsanders, srhines Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9178 llvm-svn: 235530
* Revert "[mips][FastISel] Implement shift ops for Mips fast-isel."Vasileios Kalintiris2015-04-221-122/+0
| | | | | | | This reverts commit r235194. It was causing a failure in FastISel buildbots due to sign-extension issues. llvm-svn: 235495
* [mips] Optimize code generation for 64-bit variable shift instructions.Vasileios Kalintiris2015-04-214-65/+62
| | | | | | | | | | | | | | | | Summary: The 64-bit version of the variable shift instructions uses the shift_rotate_reg class which uses a GPR32Opnd to specify the variable shift amount. With this patch we avoid the generation of a redundant SLL instruction for the variable shift instructions in 64-bit targets. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7413 llvm-svn: 235376
* [MIPS] OperationAction for FP_TO_FP16, FP16_TO_FPPirama Arumuga Nainar2015-04-201-0/+96
| | | | | | | | | | | | | | | | | | | | | | Summary: Set operation action for FP16 conversion opcodes, so the Op legalizer can choose the gnu_* libcalls for Mips. Set LoadExtAction and TruncStoreAction for f16 scalars and vectors to prevent (fpext (load )) and (store (fptrunc)) from getting combined into unsupported operations. Added test cases to test that these operations are handled correctly for f16 scalars and vectors. This patch depends on http://reviews.llvm.org/D8755. Reviewers: srhines Subscribers: llvm-commits, ab Differential Revision: http://reviews.llvm.org/D8804 llvm-svn: 235341
* [mips][FastISel] Implement FastMaterializeAlloca in Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+32
| | | | | | | | | | | | | | | | | | Summary: Implement the method FastMaterializeAlloca in Mips fast-isel Based on a patch by Reed Kotler. Test Plan: Passes test-suite at O0/O2 for mips32 r1/r2 fastalloca.ll Reviewers: dsanders, rkotler Subscribers: rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6742 llvm-svn: 235213
* [mips][FastISel] Implement shift ops for Mips fast-isel.Vasileios Kalintiris2015-04-171-0/+122
| | | | | | | | | | | | | | | | | | Summary: Add shift operators implementation to fast-isel for Mips. These are shift ops for non legal forms, i.e. i8 and i16. Based on a patch by Reed Kotler. Test Plan: Reviewers: dsanders Subscribers: echristo, rfuhler, llvm-commits Differential Revision: http://reviews.llvm.org/D6726 llvm-svn: 235194
* [mips] Teach the delay slot filler to remove needless KILL instructions.Vasileios Kalintiris2015-04-171-0/+14
| | | | | | | | | | | | | | | | | | Summary: Previously, the presence of KILL instructions would block valid candidates from filling a specific delay slot. With the elimination of the KILL instructions, in the appropriate range, we are able to fill more slots and keep the information from future def/use analysis consistent. Reviewers: dsanders Reviewed By: dsanders Subscribers: hfinkel, llvm-commits Differential Revision: http://reviews.llvm.org/D7724 llvm-svn: 235183
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-04-1646-121/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | the call instruction See r230786 and r230794 for similar changes to gep and load respectively. Call is a bit different because it often doesn't have a single explicit type - usually the type is deduced from the arguments, and just the return type is explicit. In those cases there's no need to change the IR. When that's not the case, the IR usually contains the pointer type of the first operand - but since typed pointers are going away, that representation is insufficient so I'm just stripping the "pointerness" of the explicit type away. This does make the IR a bit weird - it /sort of/ reads like the type of the first operand: "call void () %x(" but %x is actually of type "void ()*" and will eventually be just of type "ptr". But this seems not too bad and I don't think it would benefit from repeating the type ("void (), void () * %x(" and then eventually "void (), ptr %x(") as has been done with gep and load. This also has a side benefit: since the explicit type is no longer a pointer, there's no ambiguity between an explicit type and a function that returns a function pointer. Previously this case needed an explicit type (eg: a function returning a void() function was written as "call void () () * @x(" rather than "call void () * @x(" because of the ambiguity between a function returning a pointer to a void() function and a function returning void). No ambiguity means even function pointer return types can just be written alone, without writing the whole function's type. This leaves /only/ the varargs case where the explicit type is required. Given the special type syntax in call instructions, the regex-fu used for migration was a bit more involved in its own unique way (as every one of these is) so here it is. Use it in conjunction with the apply.sh script and associated find/xargs commands I've provided in rr230786 to migrate your out of tree tests. Do let me know if any of this doesn't cover your cases & we can iterate on a more general script/regexes to help others with out of tree tests. About 9 test cases couldn't be automatically migrated - half of those were functions returning function pointers, where I just had to manually delete the function argument types now that we didn't need an explicit function type there. The other half were typedefs of function types used in calls - just had to manually drop the * from those. import fileinput import sys import re pat = re.compile(r'((?:=|:|^|\s)call\s(?:[^@]*?))(\s*$|\s*(?:(?:\[\[[a-zA-Z0-9_]+\]\]|[@%](?:(")?[\\\?@a-zA-Z0-9_.]*?(?(3)"|)|{{.*}}))(?:\(|$)|undef|inttoptr|bitcast|null|asm).*$)') addrspace_end = re.compile(r"addrspace\(\d+\)\s*\*$") func_end = re.compile("(?:void.*|\)\s*)\*$") def conv(match, line): if not match or re.search(addrspace_end, match.group(1)) or not re.search(func_end, match.group(1)): return line return line[:match.start()] + match.group(1)[:match.group(1).rfind('*')].rstrip() + match.group(2) + line[match.end():] for line in sys.stdin: sys.stdout.write(conv(re.search(pat, line), line)) llvm-svn: 235145
* Re-apply r234898 and fix tests.Daniel Jasper2015-04-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit makes LLVM not estimate branch probabilities when doing a single bit bitmask tests. The code that originally made me discover this is: if ((a & 0x1) == 0x1) { .. } In this case we don't actually have any branch probability information and should not assume to have any. LLVM transforms this into: %and = and i32 %a, 1 %tobool = icmp eq i32 %and, 0 So, in this case, the result of a bitwise and is compared against 0, but nevertheless, we should not assume to have probability information. CodeGen/ARM/2013-10-11-select-stalls.ll started failing because the changed probabilities changed the results of ARMBaseInstrInfo::isProfitableToIfCvt() and led to an Ifcvt of the diamond in the test. AFAICT, the test was never meant to test this and thus changing the test input slightly to not change the probabilities seems like the best way to preserve the meaning of the test. llvm-svn: 234979
* Revert "The code that originally made me discover this is:"Rafael Espindola2015-04-141-2/+2
| | | | | | | This reverts commit r234898. CodeGen/ARM/2013-10-11-select-stalls.ll was faling. llvm-svn: 234903
* The code that originally made me discover this is:Daniel Jasper2015-04-141-2/+2
| | | | | | | | | | | | | | | | | | if ((a & 0x1) == 0x1) { .. } In this case we don't actually have any branch probability information and should not assume to have any. LLVM transforms this into: %and = and i32 %a, 1 %tobool = icmp eq i32 %and, 0 So, in this case, the result of a bitwise and is compared against 0, but nevertheless, we should not assume to have probability information. llvm-svn: 234898
* Use FileCheck for testMatthias Braun2015-04-131-13/+17
| | | | llvm-svn: 234774
* DAGCombiner: Fix crash in select(select) opt.Matthias Braun2015-04-131-0/+21
| | | | | | | | | In case of different types used for the condition of the selects the select(select) -> select(and) normalisation cannot be performed. See also: http://reviews.llvm.org/D7622 llvm-svn: 234763
* Use sext in fast isel.Rafael Espindola2015-04-061-12/+13
| | | | | | | | | | | | | | | | | | Fast isel used to zero extends immediates to 64 bits. This normally goes unnoticed because the value is truncated to 32 bits for output. Two cases were it is noticed: * We fail to use smaller encodings. * If the original constant was smaller than i32. In the tests using i1 constants, codegen would change to use -1, which is fine (and matches what regular isel does) since only the lowest bit is then used. Instead, this patch then changes the ir to use i8 constants, which looks more like what clang produces. llvm-svn: 234249
* [mips] Make sure that we don't adjust the stack pointer by zero amount.Vasileios Kalintiris2015-04-021-0/+20
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8638 llvm-svn: 233904
* [mips] Support 9-bit offsets for the 'R' inline assembly memory constraint.Daniel Sanders2015-03-302-9/+60
| | | | | | | | | | | | | | | | | | | Summary: The 'R' constraint is actually supposed to be much more complicated than this and is defined in terms of whether it will cause macro expansion in the assembler. 'R' is getting less useful due to architecture changes and ought to be replaced by other constraints. We therefore implement 9-bit offsets which will work for all subtargets and all instructions. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8440 llvm-svn: 233537
* [mips] Support 16-bit offsets for 'm' inline assembly memory constraint.Daniel Sanders2015-03-242-8/+68
| | | | | | | | | | | | Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8435 llvm-svn: 233086
* [mips] Distinguish 'R', 'ZC', and 'm' inline assembly memory constraint.Daniel Sanders2015-03-241-0/+167
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Previous behaviour of 'R' and 'm' has been preserved for now. They will be improved in subsequent commits. The offset permitted by ZC varies according to the subtarget since it is intended to match the restrictions of the pref, ll, and sc instructions. The restrictions on these instructions are: * For microMIPS: 12-bit signed offset. * For Mips32r6/Mips64r6: 9-bit signed offset. * Otherwise: 16-bit signed offset. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8414 llvm-svn: 233063
* Fix sign extension for MIPS64 in makeLibCall functionPetar Jovanovic2015-03-232-1/+215
| | | | | | | | | | | | Fixing sign extension in makeLibCall for MIPS64. In MIPS64 architecture all 32 bit arguments (int, unsigned int, float 32 (soft float)) must be sign extended. This fixes test "MultiSource/Applications/oggenc/". Patch by Strahinja Petrovic. Differential Revision: http://reviews.llvm.org/D7791 llvm-svn: 232943
* [MIPS] Fix justify error for small structuresPetar Jovanovic2015-03-161-0/+80
| | | | | | | | | | | | | | | Fix justify error for small structures bigger than 32 bits in fixed arguments for MIPS64 big endian. There was a problem when small structures are passed as fixed arguments. The structures that are bigger than 32 bits but smaller than 64 bits were not left justified properly on MIPS64 big endian. This is fixed by shifting the value to make it left justified when appropriate. Patch by Aleksandar Beserminji. Differential Revision: http://reviews.llvm.org/D8174 llvm-svn: 232382
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-03-1361-283/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gep operator Similar to gep (r230786) and load (r230794) changes. Similar migration script can be used to update test cases, which successfully migrated all of LLVM and Polly, but about 4 test cases needed manually changes in Clang. (this script will read the contents of stdin and massage it into stdout - wrap it in the 'apply.sh' script shown in previous commits + xargs to apply it over a large set of test cases) import fileinput import sys import re rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL) def conv(match): line = match.group(1) line += match.group(4) line += ", " line += match.group(2) return line line = sys.stdin.read() off = 0 for match in re.finditer(rep, line): sys.stdout.write(line[off:match.start()]) sys.stdout.write(conv(match)) off = match.end() sys.stdout.write(line[off:]) llvm-svn: 232184
* [mips][microMIPS] Make usage of NOT16 by code generatorJozef Kolek2015-03-111-0/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D7748 llvm-svn: 231963
* Reland r229944: EH: Prune unreachable resume instructions during Dwarf EH ↵Reid Kleckner2015-03-091-0/+1
| | | | | | | | | | | | preparation Fix the double-deletion of AnalysisResolver when delegating through to Dwarf EH preparation by creating one from scratch. Hopefully the new pass manager simplifies this. This reverts commit r229952. llvm-svn: 231719
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