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* [DAGCombiner] If a TokenFactor would be merged into its user, consider the ↵Nirav Dave2019-03-131-13/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | user later. Summary: A number of optimizations are inhibited by single-use TokenFactors not being merged into the TokenFactor using it. This makes we consider if we can do the merge immediately. Most tests changes here are due to the change in visitation causing minor reorderings and associated reassociation of paired memory operations. CodeGen tests with non-reordering changes: X86/aligned-variadic.ll -- memory-based add folded into stored leaq value. X86/constant-combiners.ll -- Optimizes out overlap between stores. X86/pr40631_deadstore_elision -- folds constant byte store into preceding quad word constant store. Reviewers: RKSimon, craig.topper, spatel, efriedma, courbet Reviewed By: courbet Subscribers: dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, eraman, hiraditya, kbarton, jrtc27, atanasyan, jsji, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59260 llvm-svn: 356068
* [mips] Fix encoding of the `mov.d` command for microMIPS R6Simon Atanasyan2019-03-133-98/+98
| | | | | | | | | Before this change LLVM emits non-microMIPS variant of the `mov.d` command for microMIPS code. Differential Revision: http://reviews.llvm.org/D59045 llvm-svn: 356052
* [mips] Map SW instruction to its microMIPS R6 variantSimon Atanasyan2019-03-131-0/+20
| | | | | | | | | | | | | | | | To provide mapping between standard and microMIPS R6 variants of the `sw` command we have to rename SWSP_xxx commands from "sw" to "swsp". Otherwise `tablegen` starts to show the error `Multiple matches found for `SW'`. After that to restore printing SWSP command as `sw`, I add an appropriate `MipsInstAlias` instance. We also need to implement "size reduction" for microMIPS R6. But this task is for separate patch. After that the `micromips-lwsp-swsp.ll` test case will be extended. Differential Revision: http://reviews.llvm.org/D59046 llvm-svn: 356045
* [MIPS][microMIPS] Fix PseudoMTLOHI_MM matching and expansionSimon Atanasyan2019-03-131-0/+63
| | | | | | | | | | | | | | On micromips MipsMTLOHI is always matched to PseudoMTLOHI_DSP regardless of +dsp argument. This patch checks is HasDSP predicate is present for PseudoMTLOHI_DSP so PseudoMTLOHI_MM can be matched when appropriate. Add expansion of PseudoMTLOHI_MM instruction into a mtlo/mthi pair. Patch by Mirko Brkusanin. Differential Revision: http://reviews.llvm.org/D59203 llvm-svn: 356039
* [mips] Fix CPU used in the test case to suppress warning. NFCSimon Atanasyan2019-03-131-2/+2
| | | | | | | The MSA ASE used in in the test case requires MIPS32 revision 5 or greater while the test uses MIPS32 revision 1. llvm-svn: 356038
* [MIPS][microMIPS] Add a pattern to match TruncIntFPPetar Jovanovic2019-03-111-0/+418
| | | | | | | | | | | A pattern needed to match TruncIntFP was missing. This was causing multiple tests from llvm test suite to fail during compilation for micromips. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58722 llvm-svn: 355825
* [MIPS GlobalISel] NarrowScalar G_UMULHPetar Avramovic2019-03-111-0/+67
| | | | | | | | | | NarrowScalar G_UMULH in LegalizerHelper using multiplyRegisters helper function. NarrowScalar G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58825 llvm-svn: 355815
* [MIPS GlobalISel] NarrowScalar G_MULPetar Avramovic2019-03-112-0/+263
| | | | | | | | | | | | | Narrow Scalar G_MUL for MIPS32. Revisit NarrowScalar implementation in LegalizerHelper. Introduce new helper function multiplyRegisters. It performs generic multiplication of values held in multiple registers. Generated instructions use only types NarrowTy and i1. Destination can be same or two times size of the source. Differential Revision: https://reviews.llvm.org/D58824 llvm-svn: 355814
* [MIPS GlobalISel] Fix mul operandsPetar Avramovic2019-03-074-35/+56
| | | | | | | | | | | | | | | | | Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355594
* [mips] Replace assertion by error message while lowering `RETURNADDR` and ↵Simon Atanasyan2019-03-062-0/+22
| | | | | | | | | | `FRAMEADDR` MIPS target supports lowering `RETURNADDR` and `FRAMEADDR` for a current frame only. It's better to show an error message then crash on assertion if `__builtin_return_address` is invoked with non-zero argument. llvm-svn: 355558
* Revert "[MIPS GlobalISel] Fix mul operands"Vlad Tsyrklevich2019-03-014-56/+35
| | | | | | | This reverts commit r355178, it is causing ASan failures on the sanitizer bots. llvm-svn: 355219
* [MIPS GlobalISel] Fix mul operandsPetar Avramovic2019-03-014-35/+56
| | | | | | | | | | | | | | | | | Unsigned mul high for MIPS32 is selected into two PseudoInstructions: PseudoMULTu and PseudoMFHI that use accumulator register class ACC64 for some of its operands. Registers in this class have appropriate hi and lo register as subregisters: $lo0 and $hi0 are subregisters of $ac0 etc. mul instruction implicit-defs $lo0 and $hi0 according to MipsInstrInfo.td. In functions where mul and PseudoMULTu are present fastRegisterAllocator will "run out of registers during register allocation" because 'calcSpillCost' for $ac0 will return spillImpossible because subregisters $lo0 and $hi0 of $ac0 are reserved by mul instruction above. A solution is to mark implicit-defs of $lo0 and $hi0 as dead in mul instruction. Differential Revision: https://reviews.llvm.org/D58715 llvm-svn: 355178
* [MIPS GlobalISel] Select G_UMULHPetar Avramovic2019-03-014-0/+128
| | | | | | | | Legalize G_UMULO and select G_UMULH for MIPS32. Differential Revision: https://reviews.llvm.org/D58714 llvm-svn: 355177
* [MIPS GlobalISel] Select G_UADDOPetar Avramovic2019-02-262-0/+54
| | | | | | | | | Lower G_UADDO. Legalize G_UADDO for MIPS32 Differential Revision: https://reviews.llvm.org/D58671 llvm-svn: 354900
* [mips] Emit `.module softfloat` directiveSimon Atanasyan2019-02-261-0/+8
| | | | | | | This change fixes crash on an assertion in case of using `soft float` ABI for mips32r6 target. llvm-svn: 354882
* [Mips] Fix missing masking in fast-isel of br (PR40325)Nikita Popov2019-02-252-1/+25
| | | | | | | | | | | | | | Fixes https://bugs.llvm.org/show_bug.cgi?id=40325 by zero extending (and x, 1) the condition before branching on it. To avoid regressing trivial cases, I'm combining emission of cmp+br sequences for the single-use + same block case (similar to what we do in x86). icmpbr1.ll still regresses due to the cross-bb usage of the condition. Differential Revision: https://reviews.llvm.org/D58576 llvm-svn: 354808
* [MIPS] Fix a incorrect test. (NFC)Simon Dardis2019-02-231-2/+2
| | | | | | | This test is incorrect as it should be using the microMIPSR6 instruction to return, not the microMIPS version. llvm-svn: 354726
* [mips][micromips] fix filling delay slots for PseudoIndirectBranch_MMPetar Jovanovic2019-02-221-0/+68
| | | | | | | | | | | | | | | Filling a delay slot in 32bit jump instructions with a 16bit instruction can cause issues. According to the documentation such an operation is unpredictable. This patch adds opcode Mips::PseudoIndirectBranch_MM alongside Mips::PseudoIndirectBranch and other instructions that are expanded to jr instruction and do not allow a 16bit instruction in their delay slots. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58507 llvm-svn: 354672
* [MIPS MSA] Avoid some DAG combines for vector shiftsPetar Avramovic2019-02-201-77/+56
| | | | | | | | | | DAG combiner combines two shifts into shift + and with bitmask. Avoid such combines for vectors since leaving two vector shifts as they are produces better end results. Differential Revision: https://reviews.llvm.org/D58225 llvm-svn: 354461
* [MIPS MSA] Add test for vector shift combinesPetar Avramovic2019-02-201-0/+232
| | | | | | Add test for vector shift combines. llvm-svn: 354455
* [MIPS GlobalISel] Select phi instruction for integers Petar Avramovic2019-02-144-0/+586
| | | | | | | | Select G_PHI for integers for MIPS32. Differential Revision: https://reviews.llvm.org/D58183 llvm-svn: 354025
* [MIPS GlobalISel] Select branch instructionsPetar Avramovic2019-02-144-0/+366
| | | | | | | | | | | | | Select G_BR and G_BRCOND for MIPS32. Unconditional branch G_BR does not have register operand, for that reason we only add tests. Since conditional branch G_BRCOND compares register to zero on MIPS32, explicit extension must be performed on i1 condition in order to set high bits to appropriate value. Differential Revision: https://reviews.llvm.org/D58182 llvm-svn: 354022
* [MIPS GlobalISel] Select any extending load and truncating storePetar Avramovic2019-02-084-0/+389
| | | | | | | | | | | | | | | | | | Make behavior of G_LOAD in widenScalar same as for G_ZEXTLOAD and G_SEXTLOAD. That is perform widenScalarDst to size given by the target and avoid additional checks in common code. Targets can reorder or add additional rules in LegalizeRuleSet for the opcode to achieve desired behavior. Select extending load that does not have specified type of extension into zero extending load. Select truncating store that stores number of bytes indicated by size in MachineMemoperand. Differential Revision: https://reviews.llvm.org/D57454 llvm-svn: 353520
* [MIPS GlobalISel] Select mulPetar Avramovic2019-02-084-0/+362
| | | | | | | | Legalize and select G_MUL for s32 and smaller types for MIPS32. Differential Revision: https://reviews.llvm.org/D57816 llvm-svn: 353506
* [mips][micromips] Fix how values in .gcc_except_table are calculatedPetar Jovanovic2019-02-071-4/+4
| | | | | | | | | | | | | | | | | When a landing pad is calculated in a program that is compiled for micromips with -fPIC flag, it will point to an even address. Such an error will cause a segmentation fault, as the instructions in micromips are aligned on odd addresses. This patch sets the last bit of the offset where a landing pad is, to 1, which will effectively be an odd address and point to the instruction exactly. r344591 fixed this issue for -static compilation. Patch by Aleksandar Beserminji. Differential Revision: https://reviews.llvm.org/D57677 llvm-svn: 353480
* GlobalISel: Fix creating MMOs with align 0Matt Arsenault2019-01-314-22/+22
| | | | llvm-svn: 352712
* MIR: Reject non-power-of-4 alignments in MMO parsingMatt Arsenault2019-01-308-42/+42
| | | | llvm-svn: 352686
* [mips] Support for +abs2008 attributeAleksandar Beserminji2019-01-283-21/+86
| | | | | | | | | | | | | | | | Instruction abs.[ds] is not generating correct result when working with NaNs for revisions prior mips32r6 and mips64r6. To generate a sequence which always produce a correct result, but also to allow user more control on how his code is compiled, attribute +abs2008 is added, so user can choose legacy or 2008. By default legacy mode is used on revisions prior R6. Mips32r6 and mips64r6 use abs2008 mode by default. Differential Revision: https://reviews.llvm.org/D35983 llvm-svn: 352370
* [MIPS GlobalISel] Select subPetar Avramovic2019-01-284-0/+561
| | | | | | | | | Lower G_USUBO and G_USUBE. Add narrowScalar for G_SUB. Legalize and select G_SUB for MIPS 32. Differential Revision: https://reviews.llvm.org/D53416 llvm-svn: 352351
* [MIPS GlobalISel] Select zero extending and sign extending loadPetar Avramovic2019-01-244-0/+468
| | | | | | | | | Select zero extending and sign extending load for MIPS32. Use size from MachineMemOperand to determine number of bytes to load. Differential Revision: https://reviews.llvm.org/D57099 llvm-svn: 352038
* [MIPS GlobalISel] Combine extending loadsPetar Avramovic2019-01-242-0/+238
| | | | | | | | | | | | | | Use CombinerHelper to combine extending load instructions. G_LOAD combined with G_ZEXT, G_SEXT or G_ANYEXT gives G_ZEXTLOAD, G_SEXTLOAD or G_LOAD with same type as def of extending instruction respectively. Similarly G_ZEXTLOAD combined with G_ZEXT gives G_ZEXTLOAD and G_SEXTLOAD combined with G_SEXT gives G_SEXTLOAD with same type as def of extending instruction. Differential Revision: https://reviews.llvm.org/D56914 llvm-svn: 352037
* [mips] Emit .reloc R_{MICRO}MIPS_JALR along with j(al)r(c) $25Vladimir Stefanovic2019-01-1712-95/+258
| | | | | | | | | | | | The callee address is added as an optional operand (MCSymbol) in AdjustInstrPostInstrSelection() and then used by asm printer to insert: '.reloc tmplabel, R_MIPS_JALR, symbol tmplabel:'. Controlled with '-mips-jalr-reloc', default is true. Differential revision: https://reviews.llvm.org/D56694 llvm-svn: 351485
* [MIPS GlobalISel] Fix release build make-check after r351046Petar Avramovic2019-01-141-0/+1
| | | | | | | Add 'REQUIRES: asserts' to test that uses debug output in order to fix r351046 for buildbots that use release build. llvm-svn: 351068
* [mips] Optimize shifts for types larger than GPR size (mips2/mips3)Aleksandar Beserminji2019-01-143-460/+407
| | | | | | | | | | | | | With this patch, shifts are lowered to optimal number of instructions necessary to shift types larger than the general purpose register size. This resolves PR/32293. Thanks to Kyle Butt for reporting the issue! Differential Revision: https://reviews.llvm.org/D56320 llvm-svn: 351059
* Replace "no-frame-pointer-*" function attributes with "frame-pointer"Francis Visoiu Mistrih2019-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
* [MIPS GlobalISel] Add pre legalizer combiner passPetar Avramovic2019-01-141-0/+37
| | | | | | | | | | Introduce GlobalISel pre legalizer pass for MIPS. It will be used to cope with instructions that require combining before legalization. Differential Revision: https://reviews.llvm.org/D56269 llvm-svn: 351046
* [llvm-objdump] - Implement -z/--disassemble-zeroes.George Rimar2019-01-101-2/+1
| | | | | | | | | | | | | | This is https://bugs.llvm.org/show_bug.cgi?id=37151, GNU objdump spec says that "Normally the disassembly output will skip blocks of zeroes.", but currently, llvm-objdump prints them. The patch implements the -z/--disassemble-zeroes option and switches the default to always skip blocks of zeroes. Differential revision: https://reviews.llvm.org/D56083 llvm-svn: 350823
* [MIPS GlobalISel] Select G_SELECTPetar Avramovic2018-12-254-0/+397
| | | | | | | | | | Add widen scalar for type index 1 (i1 condition) for G_SELECT. Select G_SELECT for pointer, s32(integer) and smaller low level types on MIPS32. Differential Revision: https://reviews.llvm.org/D56001 llvm-svn: 350063
* [MIPS GlobalISel] Select G_SDIV, G_UDIV, G_SREM and G_UREMPetar Avramovic2018-12-184-0/+1080
| | | | | | | | | | | | Add support for s64 libcalls for G_SDIV, G_UDIV, G_SREM and G_UREM and use integer type of correct size when creating arguments for CLI.lowerCall. Select G_SDIV, G_UDIV, G_SREM and G_UREM for types s8, s16, s32 and s64 on MIPS32. Differential Revision: https://reviews.llvm.org/D55651 llvm-svn: 349499
* [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XORPetar Avramovic2018-12-185-76/+528
| | | | | | | | | | Add narrowScalar for G_AND and G_XOR. Legalize G_AND G_OR and G_XOR for types other then s32 with clampScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D55362 llvm-svn: 349475
* [MIPS GlobalISel] Lower G_UADDE and narrowScalar G_ADDPetar Avramovic2018-12-172-9/+156
| | | | | | | | Lower G_UADDE and legalize G_ADD using narrowScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D54580 llvm-svn: 349346
* [TargetLowering] expandFP_TO_UINT - improve fp16 supportSimon Pilgrim2018-11-191-248/+48
| | | | | | | | | | As discussed on D53794, for float types with ranges smaller than the destination integer type, then we should be able to just use a regular FP_TO_SINT opcode. I thought we'd need to provide MSA test cases for very small integer types as well (fp16 -> i8 etc.), but it turns out that promotion will kick in so they're unnecessary. Differential Revision: https://reviews.llvm.org/D54703 llvm-svn: 347251
* [DAGCombiner][X86][Mips] Enable combineShuffleOfScalars to run between ↵Craig Topper2018-11-091-74/+47
| | | | | | | | | | | | vector op legalization and DAG legalization. Fix bad one use check in combineShuffleOfScalars It's possible for vector op legalization to generate a shuffle. If that happens we should give a chance for DAG combine to combine that with a build_vector input. I also fixed a bug in combineShuffleOfScalars that was considering the number of uses on a undef input to a shuffle. We don't care how many times undef is used. Differential Revision: https://reviews.llvm.org/D54283 llvm-svn: 346530
* [DAGCombine] Improve alias analysis for chain of independent stores.Nirav Dave2018-11-081-18/+18
| | | | | | | | | | | | | | | | | | | FindBetterNeighborChains simulateanously improves the chain dependencies of a chain of related stores avoiding the generation of extra token factors. For chains longer than the GatherAllAliasDepths, stores further down in the chain will necessarily fail, a potentially significant waste and preventing otherwise trivial parallelization. This patch directly parallelize the chains of stores before improving each store. This generally improves DAG-level parallelism. Reviewers: courbet, spatel, RKSimon, bogner, efriedma, craig.topper, rnk Subscribers: sdardis, javed.absar, hiraditya, jrtc27, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D53552 llvm-svn: 346432
* [MIPS GlobalISel] Set operand order for G_MERGE and G_UNMERGEPetar Avramovic2018-11-073-22/+22
| | | | | | | | | Set operands order for G_MERGE_VALUES and G_UNMERGE_VALUES so that least significant bits always go first, regardless of endianness. Differential Revision: https://reviews.llvm.org/D54098 llvm-svn: 346305
* RegAllocFast: Leave unassigned virtreg entries in mapMatthias Braun2018-11-073-43/+43
| | | | | | | | | | | | | | | | Set `LiveReg::PhysReg` to zero when freeing a register instead of removing it from the entry from `LiveRegMap`. This way no iterators get invalidated and we can avoid passing around and updating iterators all over the place. This does not change any allocator decisions. It is not completely NFC because the arbitrary iteration order through `LiveRegMap` in `spillAll()` changes so we may get a different order in those spill sequences (the amount of spills does not change). This is in preparation of https://reviews.llvm.org/D52010. llvm-svn: 346298
* [Mips] Supplement long branch pseudo instructionsStefan Maksimovic2018-11-051-8/+8
| | | | | | | | | | | Expand on LONG_BRANCH_LUi and LONG_BRANCH_(D)ADDiu pseudo instructions by creating variants which support less operands/accept GPR64Opnds as their operand in order to appease the machine verifier pass. Differential Revision: https://reviews.llvm.org/D53977 llvm-svn: 346133
* [DAGCombiner] Remove reduceBuildVecConvertToConvertBuildVec and rely on the ↵Simon Pilgrim2018-11-021-43/+108
| | | | | | | | | | | | | vectorizers instead (PR35732) reduceBuildVecConvertToConvertBuildVec vectorizes int2float in the DAGCombiner, which means that even if the LV/SLP has decided to keep scalar code using the cost models, this will override this. While there are cases where vectorization is necessary in the DAG (mainly due to legalization artefacts), I don't think this is the case here, we should assume that the vectorizers know what they are doing. Differential Revision: https://reviews.llvm.org/D53712 llvm-svn: 345964
* [mips][micromips] Fix JmpLink to TargetExternalSymbolAleksandar Beserminji2018-11-011-0/+13
| | | | | | | | | | When matching MipsISD::JmpLink t9, TargetExternalSymbol:i32'...', wrong JALR16_MM is selected. This patch adds missing pattern for JmpLink, so that JAL instruction is selected. Differential Revision: https://reviews.llvm.org/D53366 llvm-svn: 345830
* [Mips] Conditionally remove successor blockStefan Maksimovic2018-11-011-2/+2
| | | | | | | | | | | | | | | | In MipsBranchExpansion::splitMBB, upon splitting a block with two direct branches, remove the successor of the newly created block (which inherits successors from the original block) which is pointed to by the last branch in the original block only if the targets of two branches differ. This is to fix the failing test when ran with -verify-machineinstrs enabled. Differential Revision: https://reviews.llvm.org/D53756 llvm-svn: 345821
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