Commit message (Expand) | Author | Age | Files | Lines | |
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* | [mips] Explicitly select `mips32r2` CPU for test cases require 64-bit FPU. NFC | Simon Atanasyan | 2019-07-09 | 1 | -2/+2 |
* | [opaque pointer type] Add textual IR support for explicit type parameter to l... | David Blaikie | 2015-02-27 | 1 | -88/+88 |
* | [mips][msa] Build all the tests in little and big endian modes and correct an... | Daniel Sanders | 2013-11-15 | 1 | -0/+1 |
* | [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal e... | Daniel Sanders | 2013-09-27 | 1 | -1/+1 |
* | [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ft... | Daniel Sanders | 2013-08-28 | 1 | -0/+572 |
* | [mips][msa] Summarize tests | Daniel Sanders | 2013-08-28 | 1 | -0/+3 |
* | [mips][msa] Removed fcge, fcgt, fsge, fsgt | Daniel Sanders | 2013-08-20 | 1 | -176/+0 |
* | [Mips][msa] Added the simple builtins (fadd to ftq) | Jack Carter | 2013-08-15 | 1 | -0/+574 |