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path: root/llvm/test/CodeGen/Mips/atomic.ll
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* [mips] Correct label prefixes for N32 and N64.Daniel Sanders2016-07-191-69/+69
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-20/+20
* [mips][atomics] Fix atomic instruction descriptions and uses.Simon Dardis2016-06-141-10/+20
* [mips][atomics] Fix partword atomic binary operation implementationSimon Dardis2016-04-281-67/+90
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-9/+9
* CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.Tim Northover2016-03-241-2/+52
* [mips] MIPS32R6 compact branch supportDaniel Sanders2016-03-141-5/+23
* Revert "[mips] Promote the result of SETCC nodes to GPR width."Vasileios Kalintiris2016-03-011-5/+1
* [mips] Promote the result of SETCC nodes to GPR width.Vasileios Kalintiris2016-03-011-1/+5
* Revert r237789 - [mips] The naming convention for private labels is ABI depe...Daniel Sanders2015-05-201-42/+42
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-201-42/+42
* [opaque pointer type] Add textual IR support for explicit type parameter to g...David Blaikie2015-03-131-1/+1
* [opaque pointer type] Add textual IR support for explicit type parameter to l...David Blaikie2015-02-271-2/+2
* [mips][microMIPS] Fix bugs related to atomic SC/LL instructionsJozef Kolek2014-12-181-20/+33
* [mips] Promote i32 arguments to i64 for the N32/N64 ABI and fix <64-bit struc...Daniel Sanders2014-11-071-7/+7
* Replace the result usages while legalizing cmpxchg.Logan Chien2014-07-211-1/+45
* [mips] SYNC $stype instruction was added in Mips32Matheus Almeida2014-06-181-2/+2
* [mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.Daniel Sanders2014-06-161-21/+126
* [mips] Merge most of the big/little endian checks in atomic.llDaniel Sanders2014-06-161-333/+179
* IR: add "cmpxchg weak" variant to support permitted failure.Tim Northover2014-06-131-3/+6
* IR: add a second ordering operand to cmpxhg for failureTim Northover2014-03-111-3/+3
* [mips] Print instructions "beq", "bne" and "or" using assembler pseudoAkira Hatanaka2013-07-261-18/+18
* Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to f...Stephen Lin2013-07-141-20/+20
* [mips] Big-endian code generation for atomic instructions.Akira Hatanaka2013-05-311-160/+335
* [mips] Fix bug in test case. Disable machine LICM to prevent instruction fromAkira Hatanaka2012-11-021-2/+3
* Fix test cases.Akira Hatanaka2012-05-121-9/+9
* Do not replace operands of pseudo instructions with register $zero.Akira Hatanaka2012-05-111-0/+16
* Convert more tests over to the new atomic instructions.Eli Friedman2011-09-261-26/+10
* Drop support for Mips1 and Mips2.Akira Hatanaka2011-09-091-1/+1
* Lower memory barriers to sync instructions.Akira Hatanaka2011-07-191-0/+19
* Use the correct opcodes: SLLV/SRLV or AND must be used instead of SLL/SRL orAkira Hatanaka2011-07-191-16/+16
* Remove redundant instructions.Akira Hatanaka2011-07-191-10/+5
* Do not treat atomic.load.sub differently than other atomic binary intrinsics.Akira Hatanaka2011-07-181-3/+2
* Set mayLoad or mayStore flags for SC and LL in order to prevent LICM from Akira Hatanaka2011-07-181-24/+18
* This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor,Bruno Cardoso Lopes2011-05-311-0/+253
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