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* AMDGPU: Implement SGPR spilling with scalar storesMatt Arsenault2016-11-131-0/+173
| | | | | | | | | | | | | | | | nThis avoids the nasty problems caused by using memory instructions that read the exec mask while spilling / restoring registers used for control flow masking, but only for VI when these were added. This always uses the scalar stores when enabled currently, but it may be better to still try to spill to a VGPR and use this on the fallback memory path. The cache also needs to be flushed before wave termination if a scalar store is used. llvm-svn: 286766
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-111-0/+43
| | | | | | | | | | | | | | | | | | | | Summary: This pass was assuming that when a PHI instruction defined a register used by another PHI instruction that the defining insstruction would be legalized before the using instruction. This assumption was causing the pass to not legalize some PHI nodes within divergent flow-control. This fixes a bug that was uncovered by r285762. Reviewers: nhaehnle, arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D26303 llvm-svn: 286676
* AMDGPU: Preserve vcc undef flags when inverting branchMatt Arsenault2016-11-072-0/+266
| | | | | | | | | | | | | If the branch was on a read-undef of vcc, passes that used analyzeBranch to invert the branch condition wouldn't preserve the undef flag resulting in a verifier error. Fixes verifier failures in a future commit. Also fix verifier error when inserting copy for vccz corruption bug. llvm-svn: 286133
* AMDGPU: Allow additional implicit operands on MOVRELS instructionsNicolai Haehnle2016-11-021-0/+31
| | | | | | | | | | | | | | | | | | | Summary: The post-RA scheduler occasionally uses additional implicit operands when the vector implicit operand as a whole is killed, but some subregisters are still live because they are directly referenced later. Unfortunately, this seems incredibly subtle to reproduce. Fixes piglit spec/glsl-110/execution/variable-indexing/vs-temp-array-mat2-index-wr.shader_test and others. Reviewers: arsenm, tstellarAMD Subscribers: kzhuravl, wdng, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25656 llvm-svn: 285835
* AMDGPU/SI: Don't use non-0 waitcnt values when waiting on Flat instructionsTom Stellard2016-10-281-0/+59
| | | | | | | | | | | | | | Summary: Flat instruction can return out of order, so we need always need to wait for all the outstanding flat operations. Reviewers: tony-tye, arsenm Subscribers: kzhuravl, wdng, nhaehnle, llvm-commits, yaxunl Differential Revision: https://reviews.llvm.org/D25998 llvm-svn: 285479
* AMDGPU: Add definitions for scalar store instructionsMatt Arsenault2016-10-281-7/+7
| | | | | | | | | | Also add glc bit to the scalar loads since they exist on VI and change the caching behavior. This currently has an assembler bug where the glc bit is incorrectly accepted on SI/CI which do not have it. llvm-svn: 285463
* AMDGPU/SI: Handle hazard with s_rfe_b64Tom Stellard2016-10-271-0/+31
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25638 llvm-svn: 285368
* AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}laneTom Stellard2016-10-271-0/+66
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25637 llvm-svn: 285367
* AMDGPU/SI: Handle hazard with > 8 byte VMEM storesTom Stellard2016-10-271-2/+77
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25577 llvm-svn: 285359
* AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizerTom Stellard2016-10-271-49/+93
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25528 llvm-svn: 285338
* AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizerTom Stellard2016-10-151-5/+62
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye Differential Revision: https://reviews.llvm.org/D25526 llvm-svn: 284298
* [MIRParser] Parse lane masks for register live-insKrzysztof Parzyszek2016-10-121-0/+23
| | | | | | Differential Revision: https://reviews.llvm.org/D25530 llvm-svn: 284052
* Add AArch64 unit testsDiana Picus2016-10-123-208/+0
| | | | | | | | | | | | | | | Add unit tests for checking a few tricky instruction sizes. Also remove the old tests for the instruction sizes, which were clunky and brittle. Since this is the first set of target-specific unit tests, we need to add some CMake plumbing. In the future, adding unit tests for a given target will be as simple as creating a directory with the same name as the target under unittests/Target. The tests are only run if the target is enabled in LLVM_TARGETS_TO_BUILD. Differential Revision: https://reviews.llvm.org/D24548 llvm-svn: 283990
* MIRParser: Rewrite register info initialization; mostly NFCMatthias Braun2016-10-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | This changes MachineRegisterInfo to be initializes after parsing all instructions. This is in preparation for upcoming commits that allow the register class specification on the operand or deduce them from the MCInstrDesc. This commit removes the unused feature of having nonsequential register numbers. This was confusing anyway as the vreg numbers would be different after parsing when you had "holes" in your numbering. This patch also introduces the concept of an incomplete virtual register. An incomplete virtual register may be used during .mir parsing to construct MachineOperands without knowing the exact register class (or register bank) yet. NFC except for some error messages. Differential Revision: https://reviews.llvm.org/D22397 llvm-svn: 283848
* AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizerTom Stellard2016-10-071-0/+60
| | | | | | | | | | Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D25250 llvm-svn: 283622
* Move AArch64BranchRelaxation to generic codeMatt Arsenault2016-10-063-3/+3
| | | | llvm-svn: 283459
* AMDGPU: Partially fix control flow at -O0Matt Arsenault2016-09-291-0/+755
| | | | | | | | | | | | | | | Fixes to allow spilling all registers at the end of the block work with exec modifications. Don't emit s_and_saveexec_b64 for if lowering, and instead emit copies. Mark control flow mask instructions as terminators to get correct spill code placement with fast regalloc, and then have a separate optimization pass form the saveexec. This should work if SGPRs are spilled to VGPRs, but will likely fail in the case that an SGPR spills to memory and no workitem takes a divergent branch. llvm-svn: 282667
* [TargetRegisterInfo, AArch64] Add target hook for isConstantPhysReg().Geoff Berry2016-09-271-0/+48
| | | | | | | | | | | | | | | | | | | Summary: The current implementation of isConstantPhysReg() checks for defs of physical registers to determine if they are constant. Some architectures (e.g. AArch64 XZR/WZR) have registers that are constant and may be used as destinations to indicate the generated value is discarded, preventing isConstantPhysReg() from returning true. This change adds a TargetRegisterInfo hook that overrides the no defs check for cases such as this. Reviewers: MatzeB, qcolombet, t.p.northover, jmolloy Subscribers: junbuml, aemerson, mcrosier, rengolin Differential Revision: https://reviews.llvm.org/D24570 llvm-svn: 282543
* [AArch64] Simplify patchpoint/stackmap size test (r281301). NFC.Ahmed Bougacha2016-09-132-42/+0
| | | | llvm-svn: 281407
* [AArch64] Support stackmap/patchpoint in getInstSizeInBytesDiana Picus2016-09-132-0/+170
| | | | | | | | | | | | | | | | | We currently return 4 for stackmaps and patchpoints, which is very optimistic and can in rare cases cause the branch relaxation pass to fail to relax certain branches. This patch causes getInstSizeInBytes to return a pessimistic estimate of the size as the number of bytes requested in the stackmap/patchpoint. In the future, we could provide a more accurate estimate by sharing some of the logic in AArch64::LowerSTACKMAP/PATCHPOINT. Fixes part of https://llvm.org/bugs/show_bug.cgi?id=28750 Differential Revision: https://reviews.llvm.org/D24073 llvm-svn: 281301
* GlobalISel: disambiguate types when printing MIRTim Northover2016-09-122-2/+2
| | | | | | | | | | | | | | | | | Some generic instructions have multiple types. While in theory these always be discovered by inspecting the single definition of each generic vreg, in practice those definitions won't always be local and traipsing through a big function to find them will not be fun. So this changes MIRPrinter to print out the type of uses as well as defs, if they're known to be different or not known to be the same. On the parsing side, we're a little more flexible: provided each register is given a type in at least one place it's mentioned (and all types are consistent) we accept the MIR. This doesn't introduce ambiguity but makes writing tests manually a bit less painful. llvm-svn: 281204
* GlobalISel: move type information to MachineRegisterInfo.Tim Northover2016-09-092-18/+22
| | | | | | | | | | | | | | | | | We want each register to have a canonical type, which means the best place to store this is in MachineRegisterInfo rather than on every MachineInstr that happens to use or define that register. Most changes following from this are pretty simple (you need an MRI anyway if you're going to be doing any transformations, so just check the type there). But legalization doesn't really want to check redundant operands (when, for example, a G_ADD only ever has one type) so I've made use of MCInstrDesc's operand type field to encode these constraints and limit legalization's work. As an added bonus, more validation is possible, both in MachineVerifier and MachineIRBuilder (coming soon). llvm-svn: 281035
* GlobalISel: forbid physical registers on generic MIs.Tim Northover2016-08-301-10/+12
| | | | | | | | | | We're intending to move to a world where the type of a register is determined by its (unique) def. This is incompatible with physregs, which are untyped. It also means the other passes don't have to worry quite so much about register-class compatibility and inserting COPYs appropriately. llvm-svn: 280132
* MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, ↵Matthias Braun2016-08-255-24/+8
| | | | | | | | | | | | | compute it Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of running after register and simply describes that no vregs are used in a machine function. With that we can simply compute the property and do not need to dump/parse it in .mir files. Differential Revision: http://reviews.llvm.org/D23850 llvm-svn: 279698
* MIRParser/MIRPrinter: Compute HasInlineAsm instead of printing/parsing itMatthias Braun2016-08-2411-24/+0
| | | | llvm-svn: 279680
* MachineRegisterInfo/MIR: Initialize tracksSubRegLiveness early, do not ↵Matthias Braun2016-08-247-22/+4
| | | | | | | | | | | | | print/parser it tracksSubRegLiveness only depends on the Subtarget and a cl::opt, there is not need to change it or save/parse it in a .mir file. Make the field const and move the initialization LiveIntervalAnalysis to the MachineRegisterInfo constructor. Also cleanup some code and fix some instances which better use MachineRegisterInfo::subRegLivenessEnabled() instead of TargetSubtargetInfo::enableSubRegLiveness(). llvm-svn: 279676
* MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.Matthias Braun2016-08-2437-53/+2
| | | | | | | | | Specifying isSSA is an extra line at best and results in invalid MI at worst. Compute the value instead. Differential Revision: http://reviews.llvm.org/D22722 llvm-svn: 279600
* [GlobalISel] Add Selected MachineFunction property.Ahmed Bougacha2016-08-021-0/+3
| | | | | | | | | | | | | | | | Selected: the InstructionSelect pass ran and all pre-isel generic instructions have been eliminated; i.e., all instructions are now target-specific or non-pre-isel generic instructions (e.g., COPY). Since only pre-isel generic instructions can have generic virtual register operands, this also means that all generic virtual registers have been constrained to virtual registers (assigned to register classes) and that all sizes attached to them have been eliminated. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277482
* [GlobalISel] Add RegBankSelected MachineFunction property.Ahmed Bougacha2016-08-021-0/+3
| | | | | | | | | | RegBankSelected: the RegBankSelect pass ran and all generic virtual registers have been assigned to a register bank. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277475
* [GlobalISel] Add Legalized MachineFunction property.Ahmed Bougacha2016-08-021-0/+34
| | | | | | | | | | | | | Legalized: The MachineLegalizer ran; all pre-isel generic instructions have been legalized, i.e., all instructions are now one of: - generic and always legal (e.g., COPY) - target-specific - legal pre-isel generic instructions. This lets us enforce certain invariants across passes. This property is GlobalISel-specific, but is always available. llvm-svn: 277470
* [AArch64] Return the correct size for TLSDESC_CALLSEQDiana Picus2016-08-011-0/+84
| | | | | | | | | | | | | | The branch relaxation pass is computing the wrong offsets because it assumes TLSDESC_CALLSEQ eats up 4 bytes, when in fact it is lowered to an instruction sequence taking up 16 bytes. This can become a problem in huge files with lots of TLS accesses, as it may slowly move branch targets out of the range computed by the branch relaxation pass. Fixes PR24234 https://llvm.org/bugs/show_bug.cgi?id=24234 Differential Revision: https://reviews.llvm.org/D22870 llvm-svn: 277331
* CodeGen: add new "intrinsic" MachineOperand kind.Tim Northover2016-07-292-0/+37
| | | | | | | This will be used during GlobalISel, where we need a more robust and readable way to write tests than a simple immediate ID. llvm-svn: 277209
* [MIRParser] Accept unsized generic instructions.Ahmed Bougacha2016-07-282-22/+19
| | | | | | | Since r276158, we require generic instructions to have a sized type. G_BR doesn't; relax the restriction. llvm-svn: 277006
* MIRParser: Use dot instead of colon to mark subregistersMatthias Braun2016-07-264-6/+6
| | | | | | | | | | | | | | | | | Change the syntax to use `%0.sub8` to denote a subregister. This seems like a more natural fit to denote subregisters; I also plan to introduce a new ":classname" syntax in upcoming patches to denote the register class of a vreg. Note that this commit disallows plain identifiers to start with a '.' character. This shouldn't affect anything as external names/IR references are all prefixed with '$'/'%', plain identifiers are only used for instruction names, register mask names and subreg indexes. Differential Revision: https://reviews.llvm.org/D22390 llvm-svn: 276815
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-2615-57/+57
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* GlobalISel: omit braces on MachineInstr types when there's only one.Tim Northover2016-07-261-10/+10
| | | | | | Tidies up the representation a bit in the common case. llvm-svn: 276772
* GlobalISel: allow multiple types on MachineInstrs.Tim Northover2016-07-221-10/+10
| | | | llvm-svn: 276481
* GlobalISel: implement alloca instructionTim Northover2016-07-221-1/+1
| | | | llvm-svn: 276433
* [MIRTesting] Abort when failing to parse a function.Quentin Colombet2016-07-214-35/+42
| | | | | | | | | | When we failed to parse a function in the mir parser, we should abort the whole compilation instead of continuing in a weird state. Indeed, this was creating strange machine function passes failures that were hard to understand, until we notice that the function actually did not get parsed correctly! llvm-svn: 276348
* GlobalISel: implement low-level type with just size & vector lanes.Tim Northover2016-07-202-12/+12
| | | | | | | | This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158
* [GlobalISel] Mark newly-created gvregs as having a bank.Ahmed Bougacha2016-07-192-2/+28
| | | | | | | | | | Also verify that we never try to set the size of a vreg associated to a register class. Report an error when we encounter that in MIR. Fix a testcase that hit that error and had a size for no reason. llvm-svn: 276012
* llc: Add support for -run-pass noneMatthias Braun2016-07-16174-174/+174
| | | | | | | | | | This does not schedule any passes besides the ones necessary to construct and print the machine function. This is useful to test .mir file reading and printing. Differential Revision: http://reviews.llvm.org/D22432 llvm-svn: 275664
* ARM/MIR: Move test from MIR to CodeGen/ARM directoryMatthias Braun2016-07-161-164/+0
| | | | | | | | | | test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir is an actual test for the ARM load store optimization pass and not a test of the mir parser/printer. It belongs to test/CodeGen/ARM; This also updates the test to use the new -run-pass llc syntax. llvm-svn: 275662
* MIParser: reject subregister indexes on physregsMatthias Braun2016-07-161-0/+12
| | | | llvm-svn: 275658
* [MIR] Fix one GlobalISel test case that I missed in r275314.Quentin Colombet2016-07-131-3/+2
| | | | llvm-svn: 275333
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-1371-74/+74
| | | | | | | | | | | | Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
* [lanai] Update test to use peephole-opt and not peephole-optsJacques Pienaar2016-07-081-1/+1
| | | | llvm-svn: 274945
* PeepholeOptimizer: Make pass name match DEBUG_TYPEMatt Arsenault2016-07-083-8/+8
| | | | llvm-svn: 274874
* [lanai] Use peephole optimizer to generate more conditional ALU operations.Jacques Pienaar2016-07-072-0/+716
| | | | | | | | | | | | | | | | | Summary: * Similiar to the ARM backend yse the peephole optimizer to generate more conditional ALU operations; * Add predicated type with default always true to RR instructions in LanaiInstrInfo.td; * Move LanaiSetflagAluCombiner into optimizeCompare; * The ASM parser can currently only handle explicitly specified CC, so specify ".t" (true) where needed in the ASM test; * Remove unused MachineOperand flags; Reviewers: eliben Subscribers: aemerson Differential Revision: http://reviews.llvm.org/D22072 llvm-svn: 274807
* [mips][mips16] Fix machine verifier errors about incorrect register classes ↵Daniel Sanders2016-06-161-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on load/stores. Summary: [ls][bh] and [ls][bh]u cannot use sp-relative addresses and must therefore lower frameindex nodes such that there is a copy to a CPU16Regs register. This is now done consistently using a separate addressing mode that does not permit frameindex nodes. As part of this I've had to remove an optimization that reduced the number of instructions needed to work around the lack of sp-relative addresses on [ls][bh] and [ls][bh]u. This optimization used one of the eight CPU16Regs registers as a copy of the stack pointer and it's implementation was the root cause of many of the register vs register class mismatches. lw/sw can use sp-relative addresses but we ought to ensure that we use the correct version of lw/sw internally for things like IAS. This is not currently the case and this change does not fix this. However, this change does clean it up sufficiently well to fix the machine verifier failures. Also removed irrelevant functions from stchar.ll. Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21062 llvm-svn: 272882
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