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* [Hexagon] Recognize vcombine in copy propagationKrzysztof Parzyszek2016-08-021-0/+48
| | | | llvm-svn: 277528
* [Hexagon] Prefer _io over _rr for 64-bit store with constant offsetKrzysztof Parzyszek2016-08-021-0/+12
| | | | | | | | | Identify patterns where the address is aligned to an 8-byte boundary, but both the base address and the constant offset are both proper multiples of 4. In such cases, extract Base+4 into a separate instruc- tion, and use S2_storerd_io, instead of using S4_storerd_rr. llvm-svn: 277497
* [Hexagon] Generate vector printing instructionsRon Lieberman2016-08-011-0/+31
| | | | llvm-svn: 277370
* [Hexagon] Check for offset overflow when reserving scavenging slotsKrzysztof Parzyszek2016-08-011-0/+163
| | | | | | | | | Scavenging slots were only reserved when pseudo-instruction expansion in frame lowering created new virtual registers. It is possible to still need a scavenging slot even if no virtual registers were created, in cases where the stack is large enough to overflow instruction offsets. llvm-svn: 277355
* [Hexagon] Fix test that uses -debug-only to require asserts.Michael Kuperstein2016-07-291-0/+1
| | | | llvm-svn: 277218
* [Hexagon] Testcase for not merging stores into a misaligned storeKrzysztof Parzyszek2016-07-291-0/+46
| | | | | | | | | | | The DAG combiner will try to merge consecutive stores into a bigger store, unless the resulting store is not fast. Misaligned vector stores are allowed on Hexagon, but are not fast. Add a testcase to make sure this type of merging does not occur. Patch by Pranav Bhandarkar. llvm-svn: 277182
* Revert r277178, the actual change had already been appliedKrzysztof Parzyszek2016-07-291-46/+0
| | | | | | Will submit another patch with the testcase only. llvm-svn: 277180
* [Hexagon] Misaligned loads and stores are not fastKrzysztof Parzyszek2016-07-291-0/+46
| | | | | | | | | | | | The DAG combiner tries to merge stores to adjacent vector wide memory locations by creating stores which are integral multiples of the vector width. Discourage this by informing it that this is slow. This should not affect legalization passes, because all of them ignore the "Fast" argument. Patch by Pranav Bhandarkar. llvm-svn: 277178
* MachinePipeliner pass that implements Swing Modulo SchedulingBrendon Cahoon2016-07-2912-3/+456
| | | | | | | | | | | | | | | | | | | | | | | | Software pipelining is an optimization for improving ILP by overlapping loop iterations. Swing Modulo Scheduling (SMS) is an implementation of software pipelining that attempts to reduce register pressure and generate efficient pipelines with a low compile-time cost. This implementaion of SMS is a target-independent back-end pass. When enabled, the pass should run just prior to the register allocation pass, while the machine IR is in SSA form. If the pass is successful, then the original loop is replaced by the optimized loop. The optimized loop contains one or more prolog blocks, the pipelined kernel, and one or more epilog blocks. This pass is enabled for Hexagon only. To enable for other targets, a couple of target specific hooks must be implemented, and the pass needs to be called from the target's TargetMachine implementation. Differential Review: http://reviews.llvm.org/D16829 llvm-svn: 277169
* [Hexagon] Custom lower VECTOR_SHUFFLE and EXTRACT_SUBVECTOR for HVXKrzysztof Parzyszek2016-07-294-0/+432
| | | | | | | | | | | | | | | | If the mask of a vector shuffle has alternating odd or even numbers starting with 1 or 0 respectively up to the largest possible index for the given type in the given HVX mode (single of double) we can generate vpacko or vpacke instruction respectively. E.g. %42 = shufflevector <32 x i16> %37, <32 x i16> %41, <32 x i32> <i32 1, i32 3, ..., i32 63> is %42.h = vpacko(%41.w, %37.w) Patch by Pranav Bhandarkar. llvm-svn: 277168
* [Hexagon] Improve balancing of address calculationKrzysztof Parzyszek2016-07-291-0/+54
| | | | | | | | | Rebalances address calculation trees and applies Hexagon-specific optimizations to the trees to improve instruction selection. Patch by Tobias Edler von Koch. llvm-svn: 277151
* [Hexagon] Implement MI-level constant propagationKrzysztof Parzyszek2016-07-2810-2/+184
| | | | llvm-svn: 277028
* [Hexagon] Insert CFI instructions before throwing callsKrzysztof Parzyszek2016-07-281-0/+72
| | | | | | | | Normally, CFI instructions should be inserted after allocframe, but if allocframe is in the same packet with a call, the CFI instructions should be inserted before that packet. llvm-svn: 277020
* [Hexagon] Find speculative loop preheader in hardware loop generationKrzysztof Parzyszek2016-07-271-0/+44
| | | | | | | | Before adding a new preheader block, check if there is a candidate block where the loop setup could be placed speculatively. This will be off by default. llvm-svn: 276919
* [Hexagon] Do not optimize volatile stack spill slotsKrzysztof Parzyszek2016-07-271-0/+29
| | | | llvm-svn: 276916
* [Hexagon] Post-increment loads/stores enhancementsKrzysztof Parzyszek2016-07-261-0/+69
| | | | | | | - Generate vector post-increment stores more aggressively. - Predicate post-increment and vector stores in early if-conversion. llvm-svn: 276800
* [Hexagon] Gracefully handle reg class mismatch in HexagonLoopRescheduleKrzysztof Parzyszek2016-07-261-0/+30
| | | | llvm-svn: 276793
* [Hexagon] Rerun bit tracker on new instructions in RIEKrzysztof Parzyszek2016-07-261-0/+208
| | | | | | | | | | | | | | | | | | | Consider this case: vreg1 = A2_zxth vreg0 (1) ... vreg2 = A2_zxth vreg1 (2) Redundant instruction elimination could delete the instruction (1) because the user (2) only cares about the low 16 bits. Then it could delete (2) because the input is already zero-extended. The problem is that the properties allowing each individual instruction to be deleted depend on the existence of the other instruction, so either one can be deleted, but not both. The existing check for this situation in RIE was insufficient. The fix is to update all dependent cells when an instruction is removed (replaced via COPY) in RIE. llvm-svn: 276792
* [Hexagon] Bitwise operations for insert/extract word not simplifiedKrzysztof Parzyszek2016-07-262-4/+47
| | | | | | | Change the bit simplifier to generate REG_SEQUENCE instructions in addition to COPY, which will handle cases of word insert/extract. llvm-svn: 276787
* [Hexagon] Add support for proper handling of H and L constraintsKrzysztof Parzyszek2016-07-261-0/+16
| | | | | | | | | H -> High part of reg pair. L -> Low part of reg pair. Patch by Sundeep Kushwaha. llvm-svn: 276773
* [Hexagon] Add target feature to generate long callsKrzysztof Parzyszek2016-07-251-0/+73
| | | | llvm-svn: 276638
* [Hexagon] Use loop data prefetch on HexagonKrzysztof Parzyszek2016-07-221-0/+27
| | | | llvm-svn: 276422
* [Hexagon] Handle returning small structures by valueKrzysztof Parzyszek2016-07-181-0/+18
| | | | | | | This is compliant with the official ABI, but allows experimentation with calling conventions. llvm-svn: 275822
* [Hexagon] Enable .cur formation in MISched for Hexagon V60Krzysztof Parzyszek2016-07-181-0/+62
| | | | | | | | | | | Schedule a load and its use in the same packet in MISched. Previously, isResourceAvailable was returning false for dependences in the same packet, which prevented MISched from packetizing a load and its use in the same packet for v60. Patch by Ikhlas Ajbar. llvm-svn: 275804
* [Hexagon] Use timing class info as tie-breaker in machine schedulerKrzysztof Parzyszek2016-07-181-1/+1
| | | | | | Patch by Sirish Pande. llvm-svn: 275794
* [Hexagon] HexagonMachineScheduler should account for resourcesKrzysztof Parzyszek2016-07-181-1/+0
| | | | | | | | | | | | | | | | | The machine scheduler needs to account for available resources more accurately in order to avoid scheduling an instruction that forces a new packet to be created. This occurs in two ways: First, an instruction without an available resource may have a large priority due to other metrics and be scheduled when there are other instructions with available resources. Second, an instruction with a non-zero latency may become available prematurely. In both these cases, we attempt change the priority in order to allow a better instruction to be scheduled. Patch by Brendon Cahoon. llvm-svn: 275793
* [Hexagon] Fix zero latency instructions with multiple predecessorsKrzysztof Parzyszek2016-07-181-0/+1
| | | | | | | | | | | An instruction may have multiple predecessors that are candidates for using .cur. However, only one of them can use .cur in the packet. When this case occurs, we need to make sure that only one of the dependences gets a 0 latency value. Patch by Brendon Cahoon. llvm-svn: 275790
* [Hexagon] Improve patterns with stack-based addressingKrzysztof Parzyszek2016-07-153-1/+289
| | | | | | | | | - Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
* [Hexagon] Packetize function call arguments with tail call instructionsKrzysztof Parzyszek2016-07-141-0/+22
| | | | | | | | On Hexagon is it legal to packetize the instructions setting up call arguments with the call instruction itself. This was already done, except for tail calls. Make sure tail calls are handled as well. llvm-svn: 275458
* [Hexagon] Equally-sized vectors are equivalent in ISel (except vNi1)Krzysztof Parzyszek2016-06-271-0/+27
| | | | llvm-svn: 273885
* [Hexagon] Simplify (+fix) instruction selection for indexed loads/storesKrzysztof Parzyszek2016-06-241-0/+52
| | | | llvm-svn: 273733
* [Hexagon] Add SDAG preprocessing step to expose shifted addressing modesKrzysztof Parzyszek2016-06-221-0/+50
| | | | | | | | | | | Transform: (store ch addr (add x (add (shl y c) e))) to: (store ch addr (add x (shl (add y d) c))), where e = (shl d c) for some integer d. The purpose of this is to enable generation of loads/stores with shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift value c must be 0, 1 or 2. llvm-svn: 273466
* Start using shouldAssumeDSOLocal on Hexagon.Rafael Espindola2016-06-221-0/+19
| | | | | | | Include a token test showing that access to private is now the same as to internal. llvm-svn: 273457
* [Hexagon] Handle expansion of cmpxchgKrzysztof Parzyszek2016-06-221-0/+13
| | | | llvm-svn: 273432
* [Hexagon] Enable the post-RA schedulerKrzysztof Parzyszek2016-05-264-18/+9
| | | | | | | | | The aggressive anti-dependency breaker can rename the restored callee- saved registers. To prevent this, mark these registers are live on all paths to the return/tail-call instructions, and add implicit use operands for them to these instructions. llvm-svn: 270898
* When looking for a spill slot in reg scavenger, find one that matches RCKrzysztof Parzyszek2016-05-181-0/+100
| | | | | | | | | | | | When looking for an available spill slot, the register scavenger would stop after finding the first one with no register assigned to it. That slot may have size and alignment that do not meet the requirements of the register that is to be spilled. Instead, find an available slot that is the closest in size and alignment to one that is needed to spill a register from RC. Differential Revision: http://reviews.llvm.org/D20295 llvm-svn: 269969
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-181-0/+19
| | | | llvm-svn: 269933
* [Hexagon] Simplify HexagonInstrInfo::isPredicableKrzysztof Parzyszek2016-05-161-1/+1
| | | | | | | Remove all the checks for constant extenders from isPredicable. The users of it should be the ones checking cost/profitability. llvm-svn: 269664
* [Hexagon] Remove dead nodes from SelectionDAG to avoid cyclesKrzysztof Parzyszek2016-05-131-0/+18
| | | | | | | | Recent changes to the instruction selection code exposed a problem where a dead node was not removed on time. This node had both input and output chains, which lead to an apparent cycle. llvm-svn: 269458
* [Hexagon] Expand VSelect pseudo instructionsKrzysztof Parzyszek2016-05-121-0/+33
| | | | llvm-svn: 269328
* [Hexagon] Properly handle instruction selection of vsplat intrinsicsKrzysztof Parzyszek2016-05-121-0/+10
| | | | llvm-svn: 269312
* [Hexagon] Use offsets relative to FP+8 in .cfi_offset instructionsKrzysztof Parzyszek2016-05-111-0/+43
| | | | | | | | When generating .cfi_offset instructions, make sure that the offset is calculated with respect to the register used to define the CFA (which is currently always FP+8). llvm-svn: 269191
* [ScheduleDAG] Make sure to process all def operands before any use operandsKrzysztof Parzyszek2016-05-101-0/+20
| | | | | | | | | | | | | | | | | An example from Hexagon where things went wrong: %R0<def> = L2_loadrigp <ga:@fp04> ; load function address J2_callr %R0<kill>, ..., %R0<imp-def> ; call *R0, return value in R0 ScheduleDAGInstrs::buildSchedGraph would visit all instructions going backwards, and in each instruction it would visit all operands in their order on the operand list. In the case of this call, it visited the use of R0 first, then removed it from the set Uses after it visited the def. This caused the DAG to be missing the data dependence edge on R0 between the load and the call. Differential Revision: http://reviews.llvm.org/D20102 llvm-svn: 269076
* [Hexagon] Treat all conditional branches as predicted (not-taken by default)Krzysztof Parzyszek2016-05-091-1/+1
| | | | llvm-svn: 268946
* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-294-12/+124
| | | | | | Patch by Jyotsna Verma. llvm-svn: 268051
* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-282-0/+73
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-0/+151
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-0/+55
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [Tail duplication] Handle source registers with subregistersKrzysztof Parzyszek2016-04-261-0/+67
| | | | | | | | | | | | | | When a block is tail-duplicated, the PHI nodes from that block are replaced with appropriate COPY instructions. When those PHI nodes contained use operands with subregisters, the subregisters were dropped from the COPY instructions, resulting in incorrect code. Keep track of the subregister information and use this information when remapping instructions from the duplicated block. Differential Revision: http://reviews.llvm.org/D19337 llvm-svn: 267583
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-251-0/+72
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
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