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| author | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:23:10 +0000 |
|---|---|---|
| committer | Krzysztof Parzyszek <kparzysz@codeaurora.org> | 2016-07-18 14:23:10 +0000 |
| commit | 748d3efec6e14c75068c90d5439df243b39b1edb (patch) | |
| tree | 901c8862cd1de7f64b90b80852b411b3b66ce7f1 /llvm/test/CodeGen/Hexagon | |
| parent | d80f626568544e8ad041ac24076a589da27dd83d (diff) | |
| download | bcm5719-llvm-748d3efec6e14c75068c90d5439df243b39b1edb.tar.gz bcm5719-llvm-748d3efec6e14c75068c90d5439df243b39b1edb.zip | |
[Hexagon] Fix zero latency instructions with multiple predecessors
An instruction may have multiple predecessors that are candidates
for using .cur. However, only one of them can use .cur in the
packet. When this case occurs, we need to make sure that only
one of the dependences gets a 0 latency value.
Patch by Brendon Cahoon.
llvm-svn: 275790
Diffstat (limited to 'llvm/test/CodeGen/Hexagon')
| -rw-r--r-- | llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll index 6fb0a3e2658..3edf1e35d21 100644 --- a/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll +++ b/llvm/test/CodeGen/Hexagon/eliminate-pred-spill.ll @@ -1,3 +1,4 @@ +; XFAIL: * ; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-hexagon-hvx-double \ ; RUN: -hexagon-bit=0 < %s | FileCheck %s |
