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* [Hexagon] Fix packing source vectors in shufflevector selection Krzysztof Parzyszek2018-05-251-0/+12
| | | | | | | | When the shuffle mask selected a subvector of the second input vector, and aligning of the source was performed, the shuffle mask was updated incorrectly, resulting in an ICE further in the selection process. llvm-svn: 333279
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-224-72/+651
| | | | llvm-svn: 333009
* [Hexagon] Generate post-increment for floating point typesBrendon Cahoon2018-05-182-2/+87
| | | | | | | | | | The code that generates post-increments for Hexagon considered integer values only. This patch adds support to generate them for floating point values, f32 and f64. Differential Revision: https://reviews.llvm.org/D47036 llvm-svn: 332748
* [Hexagon] preserve test intent by removing undefSanjay Patel2018-05-161-3/+3
| | | | | | | | | | | | We need to clean up the DAG floating-point undef logic. This process is similar to how we handled integer undef logic in D43141. And as we did there, I'm trying to reduce the patch by changing tests that would probably become meaningless once we correct FP undef folding. llvm-svn: 332550
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-0/+204
| | | | llvm-svn: 332525
* [Hexagon] Remove unused flag from subtarget and (non)corresponding testKrzysztof Parzyszek2018-05-151-26/+0
| | | | llvm-svn: 332365
* [Hexagon] Add a target feature for memop generationKrzysztof Parzyszek2018-05-141-0/+23
| | | | llvm-svn: 332285
* Hexagon: Put relocations after instructions not packets.Sid Manning2018-05-141-1/+1
| | | | | | | | | | | | | Change relocation output so that relocation information follows individual instructions rather than clustering them at the end of packets. This change required shifting block of code but the actual change is in HexagonPrettyPrinter's PrintInst. Differential Revision: https://reviews.llvm.org/D46728 llvm-svn: 332283
* [Hexagon] Avoid predicate copies to integer registers from store-lockedKrzysztof Parzyszek2018-05-143-7/+7
| | | | llvm-svn: 332260
* [Hexagon] Add patterns for vector shift-and-accumulateKrzysztof Parzyszek2018-05-092-432/+65
| | | | llvm-svn: 331918
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-0911-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set breakpoints on labels and list source code around labels, we need collect debug information for labels, i.e., label name, the function label belong, line number in the file, and the address label located. In order to keep these information in LLVM IR and to allow backend to generate debug information correctly. We create a new kind of metadata for labels, DILabel. The format of DILabel is !DILabel(scope: !1, name: "foo", file: !2, line: 3) We hope to keep debug information as much as possible even the code is optimized. So, we create a new kind of intrinsic for label metadata to avoid the metadata is eliminated with basic block. The intrinsic will keep existing if we keep it from optimized out. The format of the intrinsic is llvm.dbg.label(metadata !1) It has only one argument, that is the DILabel metadata. The intrinsic will follow the label immediately. Backend could get the label metadata through the intrinsic's parameter. We also create DIBuilder API for labels to be used by Frontend. Frontend could use createLabel() to allocate DILabel objects, and use insertLabel() to insert llvm.dbg.label intrinsic in LLVM IR. Differential Revision: https://reviews.llvm.org/D45024 Patch by Hsiangkai Wang. llvm-svn: 331841
* [Hexagon] Handle non-immediate constants in HexagonSplitDoubleKrzysztof Parzyszek2018-05-041-0/+24
| | | | llvm-svn: 331527
* [Hexagon] Skip reserved physical registers when updating livenessKrzysztof Parzyszek2018-05-041-0/+30
| | | | llvm-svn: 331518
* [LivePhysRegs] Remove registers clobbered by regmasks from the live setKrzysztof Parzyszek2018-04-301-0/+39
| | | | | | | | Dead defs were being removed from the live set (in stepForward), but registers clobbered by regmasks weren't (more specifically, they were actually removed by removeRegsInMask, but then they were added back in). llvm-svn: 331219
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-202-0/+76
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Skip fixed-stack indexes in HexagonConstExtendersKrzysztof Parzyszek2018-04-201-0/+51
| | | | | | | Fixed slots have negative values, and TRI::stackSlot2Index and TRI::index2StackSlot do not handle negative numbers. llvm-svn: 330468
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-0/+25
| | | | | | | | | | This fixes https://llvm.org/PR36825. Original patch by Valentin Churavy (D45218). Differential Revision: https://reviews.llvm.org/D45731 llvm-svn: 330345
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+34
| | | | llvm-svn: 330344
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+45
| | | | llvm-svn: 330333
* [Hexagon] Add/fix patterns for 32/64-bit vector compares and logical opsKrzysztof Parzyszek2018-04-194-3/+356
| | | | llvm-svn: 330330
* [Hexagon] Do not merge initializers for stack and non-stack expressionsKrzysztof Parzyszek2018-04-171-0/+35
| | | | | | | | | Stack addressing needs addressing modes that provide an offset field immediately following the frame index. An initializer from a non-stack addressing could force the stack address to use a form that does not provide an offset field. llvm-svn: 330191
* Disable flaky tests till they get fixed.Galina Kistanova2018-04-102-1/+2
| | | | llvm-svn: 329763
* [Hexagon] Handle subregisters when calculating iteration count in HW loopsKrzysztof Parzyszek2018-04-061-0/+30
| | | | llvm-svn: 329434
* [Hexagon] Remove unneeded attributes from lit testKrzysztof Parzyszek2018-04-031-1/+1
| | | | llvm-svn: 329078
* [Hexagon] Fix testcaseKrzysztof Parzyszek2018-03-301-1/+1
| | | | llvm-svn: 328899
* [Hexagon] Avoid creating invalid offsets in packetizerKrzysztof Parzyszek2018-03-301-0/+34
| | | | | | | | | | Two memory instructions with a dependency only on the address register between the two (the first one of them being post-incrememnt) can be packetized together after the offset on the second was updated to the incremement value. Make sure that the new offset is valid for the instruction. llvm-svn: 328897
* [Hexagon] Fix printing :mem_noshuf on compiler-generated packetsKrzysztof Parzyszek2018-03-301-0/+46
| | | | llvm-svn: 328869
* [Hexagon] Add support to handle bit-reverse load intrinsicsKrzysztof Parzyszek2018-03-292-111/+63
| | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 328774
* [Hexagon] Add support for "new" circular buffer intrinsicsKrzysztof Parzyszek2018-03-281-0/+294
| | | | | | | | | | | | | | | | | | | These instructions have been around for a long time, but we haven't supported intrinsics for them. The "new" versions use the CSx register for the start of the buffer instead of the K field in the Mx register. We need to use pseudo instructions for these instructions until after register allocation. The problem is that these instructions allocate a M0/CS0 or M1/CS1 pair. But, we can't generate code for the CSx set-up until after register allocation when the Mx register has been fixed for the instruction. There is a related clang patch. Patch by Brendon Cahoon. llvm-svn: 328724
* [Hexagon] Implement TTI::shouldMaximizeVectorBandwidthKrzysztof Parzyszek2018-03-271-0/+47
| | | | llvm-svn: 328648
* [Hexagon] Add more lit testsKrzysztof Parzyszek2018-03-2612-0/+1367
| | | | llvm-svn: 328561
* [Pipeliner] Add missing loop carried dependencesKrzysztof Parzyszek2018-03-261-0/+54
| | | | | | | | | | | | | | | | | | | | | | The pipeliner is not adding a dependence edge for a loop carried dependence, and ends up scheduling a load from iteration n prior to an aliased store in iteration n-1. The code that adds the loop carried dependences in the pipeliner doesn't check if the memory objects for loads and stores are "identified" (i.e., distinct) objects. If they are not, then the code that adds the dependences needs to be conservative. The objects can be used to check dependences only when they are distinct objects. The code that checks for loop carried dependences has been updated to classify loads and stores that are not identified as "unknown" values. A store with an "unknown" value can potentially create a loop carried dependence with any pending load. Patch by Brendon Cahoon. llvm-svn: 328547
* [Pipeliner] Use latency to compute RecMIIKrzysztof Parzyszek2018-03-262-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch contains severals changes needed to pipeline an example that was transformed so that a Phi with a subreg is converted to copies. The pipeliner wasn't working for a couple of reasons. - The RecMII was 3 instead of 2 due to the extra copies. - Copy instructions contained a latency of 1. - The node order algorithm was not choosing the best "bottom" node, which caused an instruction to be scheduled that had a predecessor and successor already scheduled. - Updated the Hexagon Machine Scheduler to check if the node is latency bound when adding the cost for a 0-latency dependence. The RecMII was 3 because the computation looks at the number of nodes in the recurrence. The extra copy is an extra node but it shouldn't increase the latency. The new RecMII computation looks at the latency of the instructions in the recurrence. We changed the latency of the dependence of a copy to 0. The latency computation for the copy also checks the use of the copy (similar to a reg_sequence). The node order algorithm was not choosing the last instruction in the recurrence for a bottom up traversal. This was when the last instruction is a copy. A check was added when choosing the instruction to check for NodeNum if the maxASAP is the same. This means that the scheduler will not end up with another node in the recurrence that has both a predecessor and successor already scheduled. The cost computation in Hexagon Machine Scheduler adds cost when an instruction can be packetized with a zero-latency instruction. We should only do this if the schedule is latency bound. Patch by Brendon Cahoon. llvm-svn: 328542
* [Pipeliner] Fix assert caused by pipeliner serializationKrzysztof Parzyszek2018-03-261-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The pipeliner is asserting because the serialization step that occurs at the end is deleting an instruction. The assert occurs later on because there is a use without a definition. The problem occurs when an instruction defines a value used by a REQ_SEQUENCE and that value is used by a COPY instruction. The latencies between these instructions are zero, so they are put in to the same packet. The serialization code is unable to handle this correctly, and ends up putting the REG_SEQUENCE before its definition. There is special code in the serialization step that attempts to handle zero-cost instructions (phis, copy, reg_sequence) differently than regular instructions. Unfortunately, this means the order does not come out correct. This patch simplifies the code by changing the seperate steps for handling zero-cost and regular instructions. Only phis are handled separate now, since they should occurs first. Then, this patch adds checks to make use the MoveUse is set to the smallest value if there are multiple uses in a cycle. Patch by Brendon Cahoon. llvm-svn: 328540
* [Pipeliner] Fix check for order dependences when finalizing instructionsKrzysztof Parzyszek2018-03-261-0/+51
| | | | | | | | | | | | | | | | | The code in orderDepdences that looks at the order dependences between instructions was processing all the successor and predecessor order dependences. However, we really only want to check for an order dependence for instructions scheduled in the same cycle. Also, fixed how the pipeliner handles output dependences. An output dependence is also a potential loop carried dependence. The pipeliner didn't handle this case properly so an invalid schedule could be created that allowed an output dependence to be scheduled in the next iteration at the same cycle. Patch by Brendon Cahoon. llvm-svn: 328516
* [Pipeliner] Fix in the pipeliner phi reuse codeKrzysztof Parzyszek2018-03-261-0/+44
| | | | | | | | | | | When the definition of a phi is used by a phi in the next iteration, the pipeliner was assuming that the definition is processed first. Because of the assumption, an incorrect phi name was used. This patch has a check to see if the phi definition has been processed already. Patch by Brendon Cahoon. llvm-svn: 328510
* [Pipeliner] Correctly update memoperands in the epilogKrzysztof Parzyszek2018-03-261-0/+102
| | | | | | | | | | | | | | | | The pipeliner needs to be conservative when updating the memoperands of instructions in the epilog. Previously, the pipeliner was changing the offset of the memoperand based upon the scheduling stage. However, that is incorrect when control flow branches around the kernel code. The bug enabled a load and store to the same stack offset to be swapped. This patch fixes the bug by updating the size of the memoperands to be UINT_MAX. This conservative value means that dependences will be created between other loads and stores. Patch by Brendon Cahoon. llvm-svn: 328508
* [Hexagon] Give priority to post-incremementing memory accesses in LSRKrzysztof Parzyszek2018-03-264-43/+47
| | | | llvm-svn: 328506
* [Hexagon] Boost profit for word-mask immediates, reduce for othersKrzysztof Parzyszek2018-03-232-0/+145
| | | | | | This avoids unnecessary splitting due to uninteresting immediates. llvm-svn: 328364
* [Hexagon] Fold offset in base+immediate loads/storesKrzysztof Parzyszek2018-03-231-0/+55
| | | | | | | | Optimize Ry = add(Rx,#n); memw(Ry+#0) = Rz => memw(Rx,#n) = Rz. Patch by Jyotsna Verma. llvm-svn: 328355
* [Hexagon] Always generate mux out of predicated transfers if possibleKrzysztof Parzyszek2018-03-236-3/+64
| | | | | | | | | | | | HexagonGenMux would collapse pairs of predicated transfers if it assumed that the predicated .new forms cannot be created. Turns out that generating mux is preferable in almost all cases. Introduce an option -hexagon-gen-mux-threshold that controls the minimum distance between the instruction defining the predicate and the later of the two transfers. If the distance is closer than the threshold, mux will not be generated. Set the threshold to 0 by default. llvm-svn: 328346
* [Hexagon] Avoid early if-conversion for one sided branchesKrzysztof Parzyszek2018-03-231-0/+80
| | | | | | Patch by Anand Kodnani. llvm-svn: 328344
* [Hexagon] Two fixes in early if-conversionKrzysztof Parzyszek2018-03-231-0/+75
| | | | | | | | | - Fix checking for vector predicate registers. - Avoid speculating llvm.lifetime.end intrinsic. Patch by Harsha Jagasia and Brendon Cahoon. llvm-svn: 328339
* [CodeGen] Add a new pass for PostRA sinkJun Bum Lim2018-03-222-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This pass sinks COPY instructions into a successor block, if the COPY is not used in the current block and the COPY is live-in to a single successor (i.e., doesn't require the COPY to be duplicated). This avoids executing the the copy on paths where their results aren't needed. This also exposes additional opportunites for dead copy elimination and shrink wrapping. These copies were either not handled by or are inserted after the MachineSink pass. As an example of the former case, the MachineSink pass cannot sink COPY instructions with allocatable source registers; for AArch64 these type of copy instructions are frequently used to move function parameters (PhyReg) into virtual registers in the entry block.. For the machine IR below, this pass will sink %w19 in the entry into its successor (%bb.1) because %w19 is only live-in in %bb.1. ``` %bb.0: %wzr = SUBSWri %w1, 1 %w19 = COPY %w0 Bcc 11, %bb.2 %bb.1: Live Ins: %w19 BL @fun %w0 = ADDWrr %w0, %w19 RET %w0 %bb.2: %w0 = COPY %wzr RET %w0 ``` As we sink %w19 (CSR in AArch64) into %bb.1, the shrink-wrapping pass will be able to see %bb.0 as a candidate. With this change I observed 12% more shrink-wrapping candidate and 13% more dead copies deleted in spec2000/2006/2017 on AArch64. Reviewers: qcolombet, MatzeB, thegameg, mcrosier, gberry, hfinkel, john.brawn, twoh, RKSimon, sebpop, kparzysz Reviewed By: sebpop Subscribers: evandro, sebpop, sfertile, aemerson, mgorny, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D41463 llvm-svn: 328237
* [Hexagon] Eliminate subregisters from PHI nodes before pipeliningKrzysztof Parzyszek2018-03-211-3/+3
| | | | | | | | | | | | | | | | The pipeliner needs to remove instructions from the SlotIndexes structure when they are deleted. Otherwise, the SlotIndexes map has stale data, and an assert will occur when adding new instructions. This patch also changes the pipeliner to make the back-edge of a loop carried dependence 1 cycle. The 1 cycle latency is added to the anti-dependence that represents the back-edge. This changes eliminates a couple of hacks added to the pipeliner to handle the latency of the back-edge. It is needed to correctly pipeline the test case for the sub-register elimination pass. llvm-svn: 328113
* [Hexagon] Add a few more lit tests, NFCKrzysztof Parzyszek2018-03-2014-0/+1134
| | | | llvm-svn: 328023
* [Hexagon] Add heuristic to exclude critical path cost for schedulingKrzysztof Parzyszek2018-03-204-7/+9
| | | | | | Patch by Brendon Cahoon. llvm-svn: 328022
* [Hexagon] Correct the computation of TopReadyCycle and BotReadyCycle of SUKrzysztof Parzyszek2018-03-201-1/+0
| | | | | | | | | TopReadyCycle and BotReadyCycle were off by one cycle when an SU is either the first instruction or the last instruction in a packet. Patch by Ikhlas Ajbar. llvm-svn: 328000
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-203-5/+7
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327975
* [Hexagon] Add REQUIRES: asserts to test/CodeGen/Hexagon/v6vec_inc1.llKrzysztof Parzyszek2018-03-191-0/+1
| | | | llvm-svn: 327907
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