[Hexagon] Improve HVX instruction selection (bitcast, vsplat)

There was some unfortunate interaction between VSPLAT and BITCAST
related to the selection of constant vectors (coming from selecting
shuffles). Introduce VSPLATW that always splats a 32-bit word, and
can have arbitrary result type (to avoid BITCASTs of VSPLAT).
Clean up the previous selection of BITCAST/VSPLAT.

llvm-svn: 330471

2 files changed, 76 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
new file mode 100644
index 00000000000..94b77bf7f80
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat.ll
@@ -0,0 +1,50 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; This testcase exposed a problem with a previous handling of selecting
+; constant vectors (for vdelta). Originally a bitcast of a vsplat was
+; created (both being ISD, not machine nodes). Selection of vsplat relies
+; on its return type, and there was no way to get these nodes to be
+; selected in the right order, without getting the main selection algorithm
+; confused.
+
+; Make sure this compiles successfully.
+; CHECK: call f1
+
+target triple = "hexagon"
+
+%s.0 = type { %s.1 }
+%s.1 = type { i32, i8* }
+%s.2 = type { i8, i8, [16 x i8], i8, [16 x i8] }
+
+; Function Attrs: nounwind
+define dso_local zeroext i8 @f0(i8 zeroext %a0, %s.2* nocapture readonly %a1, i8 signext %a2) local_unnamed_addr #0 {
+b0:
+  br i1 undef, label %b2, label %b1
+
+b1:                                               ; preds = %b0
+  %v0 = load <64 x i8>, <64 x i8>* undef, align 1
+  %v1 = icmp ult <64 x i8> %v0, <i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52, i8 52>
+  %v2 = xor <64 x i1> %v1, zeroinitializer
+  %v3 = select <64 x i1> %v2, <64 x i32> undef, <64 x i32> zeroinitializer
+  %v4 = select <64 x i1> zeroinitializer, <64 x i32> <i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000, i32 304000>, <64 x i32> %v3
+  %v5 = add <64 x i32> %v4, zeroinitializer
+  br label %b2
+
+b2:                                               ; preds = %b1, %b0
+  %v6 = phi <64 x i32> [ undef, %b0 ], [ %v5, %b1 ]
+  %v7 = add <64 x i32> %v6, undef
+  %v8 = add <64 x i32> %v7, undef
+  %v9 = add <64 x i32> %v8, undef
+  %v10 = add <64 x i32> %v9, undef
+  %v11 = add <64 x i32> %v10, undef
+  %v12 = add <64 x i32> %v11, undef
+  %v13 = extractelement <64 x i32> %v12, i32 0
+  tail call void @f1(%s.0* null, i32 undef, i32 undef, i32 %v13, i32 undef) #2
+  unreachable
+}
+
+declare dso_local void @f1(%s.0*, i32, i32, i32, i32) local_unnamed_addr #1
+
+attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
+attributes #1 = { "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }
+attributes #2 = { nounwind }
diff --git a/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
new file mode 100644
index 00000000000..691ca825615
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/autohvx/isel-bitcast-vsplat2.ll
@@ -0,0 +1,26 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; Check that this compiles successfully.
+; CHECK: vsplat
+
+target triple = "hexagon"
+
+; Function Attrs: norecurse nounwind
+define dso_local i32 @f0(i32* nocapture %a0, i32* nocapture readonly %a1, i32* nocapture readonly %a2, i32 %a3) local_unnamed_addr #0 {
+b0:
+  %v0 = insertelement <16 x i32> undef, i32 %a3, i32 0
+  %v1 = shufflevector <16 x i32> %v0, <16 x i32> undef, <16 x i32> zeroinitializer
+  %v2 = add i32 %a3, 64
+  %v3 = add <16 x i32> %v1, <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
+  %v4 = sdiv <16 x i32> %v3, <i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23, i32 23>
+  %v5 = add nsw <16 x i32> %v4, <i32 1000, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
+  %v6 = shufflevector <16 x i32> %v5, <16 x i32> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
+  %v7 = add <16 x i32> %v5, %v6
+  %v8 = extractelement <16 x i32> %v7, i32 0
+  %v9 = add nsw i32 %v2, 1
+  %v10 = sdiv i32 %v9, 23
+  %v11 = add i32 %v8, %v10
+  ret i32 %v11
+}
+
+attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" }