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* [Hexagon] Optimize addressing modes for load/storeKrzysztof Parzyszek2016-04-294-12/+124
| | | | | | Patch by Jyotsna Verma. llvm-svn: 268051
* [RDF] Improve handling of inline-asmKrzysztof Parzyszek2016-04-282-0/+73
| | | | | | | - Keep implicit defs from inline-asm instructions. - Treat register references from inline-asm as fixed. llvm-svn: 267936
* Reset the TopRPTracker's position in ScheduleDAGMILive::initQueuesKrzysztof Parzyszek2016-04-281-0/+151
| | | | | | | | | | | | | | | | | | | ScheduleDAGMI::initQueues changes the RegionBegin to the first non-debug instruction. Since it does not track register pressure, it does not affect any RP trackers. ScheduleDAGMILive inherits initQueues from ScheduleDAGMI, and it does reset the TopTPTracker in its schedule method. Any derived, target-specific scheduler will need to do it as well, but the TopRPTracker is only exposed as a "const" object to derived classes. Without the ability to modify the tracker directly, this leaves a derived scheduler with a potential of having the TopRPTracker out-of-sync with the CurrentTop. The symptom of the problem: void llvm::ScheduleDAGMILive::scheduleMI(llvm::SUnit *, bool): Assertion `TopRPTracker.getPos() == CurrentTop && "out of sync"' failed. Differential Revision: http://reviews.llvm.org/D19438 llvm-svn: 267918
* [RDF] Handle undefined registers in RDF copy propagationKrzysztof Parzyszek2016-04-281-0/+55
| | | | | | | When updating the graph, make sure that new uses without reaching defs are handled correctly. llvm-svn: 267891
* [Tail duplication] Handle source registers with subregistersKrzysztof Parzyszek2016-04-261-0/+67
| | | | | | | | | | | | | | When a block is tail-duplicated, the PHI nodes from that block are replaced with appropriate COPY instructions. When those PHI nodes contained use operands with subregisters, the subregisters were dropped from the COPY instructions, resulting in incorrect code. Keep track of the subregister information and use this information when remapping instructions from the duplicated block. Differential Revision: http://reviews.llvm.org/D19337 llvm-svn: 267583
* [Hexagon] Register save/restore functions do not follow regular conventionsKrzysztof Parzyszek2016-04-251-0/+72
| | | | | | Do not mark them as modifying any of the volatile registers by default. llvm-svn: 267433
* [Hexagon] Properly close live range in HexagonBlockRanges ---add testcaseKrzysztof Parzyszek2016-04-221-0/+55
| | | | llvm-svn: 267174
* [Hexagon] Teach mux expansion how to deal with undef predicatesKrzysztof Parzyszek2016-04-221-0/+22
| | | | llvm-svn: 267165
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-215-5/+88
| | | | llvm-svn: 267034
* [RDF] Consider register as live if any alias is liveKrzysztof Parzyszek2016-04-201-0/+28
| | | | | | This only affects the recomputation of kill flags. llvm-svn: 266875
* [Hexagon] Fix operand swapping in HexagonPeepholeKrzysztof Parzyszek2016-04-191-0/+30
| | | | | | Also, disable zero- and size-extend optimizations for now. llvm-svn: 266821
* [Hexagon] Fix printing the address operand of S2_storerinewabsKrzysztof Parzyszek2016-04-192-1/+17
| | | | llvm-svn: 266811
* [PR27284] Reverse the ownership between DICompileUnit and DISubprogram.Adrian Prantl2016-04-152-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently each Function points to a DISubprogram and DISubprogram has a scope field. For member functions the scope is a DICompositeType. DIScopes point to the DICompileUnit to facilitate type uniquing. Distinct DISubprograms (with isDefinition: true) are not part of the type hierarchy and cannot be uniqued. This change removes the subprograms list from DICompileUnit and instead adds a pointer to the owning compile unit to distinct DISubprograms. This would make it easy for ThinLTO to strip unneeded DISubprograms and their transitively referenced debug info. Motivation ---------- Materializing DISubprograms is currently the most expensive operation when doing a ThinLTO build of clang. We want the DISubprogram to be stored in a separate Bitcode block (or the same block as the function body) so we can avoid having to expensively deserialize all DISubprograms together with the global metadata. If a function has been inlined into another subprogram we need to store a reference the block containing the inlined subprogram. Attached to https://llvm.org/bugs/show_bug.cgi?id=27284 is a python script that updates LLVM IR testcases to the new format. http://reviews.llvm.org/D19034 <rdar://problem/25256815> llvm-svn: 266446
* Revert r265817Colin LeMahieu2016-04-082-2/+2
| | | | | | lld tests need to be addressed. llvm-svn: 265822
* [llvm-objdump] Printing hex instead of dec by defaultColin LeMahieu2016-04-082-2/+2
| | | | | | Differential Revision: http://reviews.llvm.org/D18770 llvm-svn: 265817
* testcase gardening: update the emissionKind enum to the new syntax. (NFC)Adrian Prantl2016-04-012-2/+2
| | | | llvm-svn: 265081
* [Hexagon] Improve handling of unaligned vector loads and storesKrzysztof Parzyszek2016-03-281-0/+31
| | | | llvm-svn: 264584
* [Hexagon] Only use restore functions for single register at -OzKrzysztof Parzyszek2016-03-281-0/+42
| | | | llvm-svn: 264581
* [Hexagon] Add support for run-time stack overflow checkingKrzysztof Parzyszek2016-03-241-0/+44
| | | | | | Patch by Sundeep Kushwaha. llvm-svn: 264328
* [Hexagon] Generate PIC-specific versions of save/restore routinesKrzysztof Parzyszek2016-03-241-0/+69
| | | | | | | | | | | | In PIC mode, the registers R14, R15 and R28 are reserved for use by the PLT handling code. This causes all functions to clobber these registers. While this is not new for regular function calls, it does also apply to save/restore functions, which do not follow the standard ABI conventions with respect to the volatile/non-volatile registers. Patch by Jyotsna Verma. llvm-svn: 264324
* Fix tests that used CHECK-NEXT-NOT and CHECK-DAG-NOT.Paul Robinson2016-02-262-2/+2
| | | | | | | | FileCheck actually doesn't support combo suffixes. Differential Revision: http://reviews.llvm.org/D17588 llvm-svn: 262054
* [Hexagon] Implement TLS supportKrzysztof Parzyszek2016-02-182-0/+65
| | | | | | Patch by Anand Kodnani. llvm-svn: 261218
* [Hexagon] Add support for __builtin_prefetchKrzysztof Parzyszek2016-02-183-0/+70
| | | | llvm-svn: 261210
* [Hexagon] Missed testcase update in r260895Krzysztof Parzyszek2016-02-151-1/+1
| | | | llvm-svn: 260897
* [Hexagon] Use zero-extending loads for anyextKrzysztof Parzyszek2016-02-151-1/+1
| | | | llvm-svn: 260895
* [Hexagon] Optimize stack slot spillsKrzysztof Parzyszek2016-02-125-3/+353
| | | | | | | | | | | | | | Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
* [Hexagon] Replace expansion of spill pseudo-instructions in frame loweringKrzysztof Parzyszek2016-02-121-0/+3
| | | | | | | | | Rewrite the code to handle all pseudo-instructions in a single pass. This temporarily reverts spill slot optimization that used general- purpose registers to hold values of spilled predicate registers. llvm-svn: 260696
* [Hexagon] Eliminate pseudo instructions for circ/brev loads and storesKrzysztof Parzyszek2016-02-124-55/+36
| | | | | | | | | We can generate the actual instructions from the intrinsics without the need for pseudo-instructions. Also, since the intrinsics have a side- effect in a form of a store, attempt to optimize away loads from the store location. llvm-svn: 260690
* [Hexagon] Specify vector alignment in DataLayout stringKrzysztof Parzyszek2016-02-121-0/+38
| | | | | | | | | | | The DataLayout can calculate alignment of vectors based on the alignment of the element type and the number of elements. In fact, it is the product of these two values. The problem is that for vectors of N x i1, this will return the alignment of N bytes, since the alignment of i1 is 8 bits. The vector types of vNi1 should be aligned to N bits instead. Provide explicit alignment for HVX vectors to avoid such complications. llvm-svn: 260678
* The canonical way to XFAIL a test for all targets is XFAIL: *, not XFAIL:Benjamin Kramer2016-02-041-1/+1
| | | | | | | | Fix the lit bug that enabled this "feature" (empty triple is substring of all possible target triples) and change the two outliers to use the documented * syntax. llvm-svn: 259799
* [Hexagon] Use general purpose registers to spill pred/mod registers intoKrzysztof Parzyszek2016-01-221-0/+42
| | | | | | Patch by Tobias Edler Von Koch. llvm-svn: 258527
* Proper handling of diamond-like cases in if-conversionKrzysztof Parzyszek2016-01-201-0/+43
| | | | | | | | | | | If converter was somewhat careless about "diamond" cases, where there was no join block, or in other words, where the true/false blocks did not have analyzable branches. In such cases, it was possible for it to remove (needed) branches, resulting in a loss of entire basic blocks. Differential Revision: http://reviews.llvm.org/D16156 llvm-svn: 258310
* [Hexagon] Generate CONST64 when optimizing for size in copy-to-combineKrzysztof Parzyszek2016-01-151-0/+18
| | | | llvm-svn: 257891
* [Hexagon] Use S2_lsr_i_r instead of S2_extractu to obtain upper halfwordKrzysztof Parzyszek2016-01-141-0/+13
| | | | llvm-svn: 257815
* [Hexagon] Expand pseudo instruction Insert4Krzysztof Parzyszek2016-01-141-0/+112
| | | | llvm-svn: 257771
* [Hexagon] Handle branches with non-mbb operandsKrzysztof Parzyszek2016-01-141-0/+46
| | | | llvm-svn: 257768
* [Hexagon] Do not insert non-phis before phis in bit simplificationKrzysztof Parzyszek2016-01-131-0/+58
| | | | llvm-svn: 257606
* [Hexagon] Implement RDF-based post-RA optimizationsKrzysztof Parzyszek2016-01-123-1/+87
| | | | | | | | - Handle simple cases of register copies (what current RDF CP allows). - Hexagon-specific dead code elimination: handles dead address updates in post-increment instructions. llvm-svn: 257504
* [Hexagon] Add PIC supportKrzysztof Parzyszek2015-12-183-0/+91
| | | | llvm-svn: 256025
* [Hexagon] Make memcpy lowering thread-safeTobias Edler von Koch2015-12-161-0/+32
| | | | | | | | This removes an unpleasant hack involving a global variable for special lowering of certain memcpy calls. These are now lowered as intended in EmitTargetCodeForMemcpy in the same way that other targets do it. llvm-svn: 255785
* [Hexagon] Preprocess mapped instructions before lowering to MCKrzysztof Parzyszek2015-12-154-6/+6
| | | | llvm-svn: 255653
* [Hexagon] Add NewValueJump support for C4_cmpneq, C4_cmplte, C4_cmplteuRon Lieberman2015-12-081-0/+89
| | | | llvm-svn: 255027
* [Hexagon] Adding v60 test, vasr in particular.Ron Lieberman2015-12-071-0/+247
| | | | llvm-svn: 254923
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. (This is the second attempt to submit this patch. The first caused two assertion failures and was reverted. See https://llvm.org/bugs/show_bug.cgi?id=25687) The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254377
* Revert r254348: "Replace all weight-based interfaces in MBB with ↵Hans Wennborg2015-12-011-1/+1
| | | | | | | | | | probability-based interfaces, and update all uses of old interfaces." and the follow-up r254356: "Fix a bug in MachineBlockPlacement that may cause assertion failure during BranchProbability construction." Asserts were firing in Chromium builds. See PR25687. llvm-svn: 254366
* Replace all weight-based interfaces in MBB with probability-based ↵Cong Hou2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interfaces, and update all uses of old interfaces. The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes (http://reviews.llvm.org/D13908). 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights (http://reviews.llvm.org/D14361). 3. Use new interfaces in all other passes. 4. Remove old interfaces. This patch is 3+4 above. In this patch, MBB won't provide weight-based interfaces any more, which are totally replaced by probability-based ones. The interface addSuccessor() is redesigned so that the default probability is unknown. We allow unknown probabilities but don't allow using it together with known probabilities in successor list. That is to say, we either have a list of successors with all known probabilities, or all unknown probabilities. In the latter case, we assume each successor has 1/N probability where N is the number of successors. An assertion checks if the user is attempting to add a successor with the disallowed mixed use as stated above. This can help us catch many misuses. All uses of weight-based interfaces are now updated to use probability-based ones. Differential revision: http://reviews.llvm.org/D14973 llvm-svn: 254348
* [Hexagon] Hexagon V60 HVX intrinsic defintionsKrzysztof Parzyszek2015-11-262-0/+2610
| | | | | Author: Ron Lieberman <ronl@codeaurora.org> llvm-svn: 254165
* Add hexagonv55 and hexagonv60 as recognized CPUs, make v60 the defaultKrzysztof Parzyszek2015-11-254-4/+4
| | | | llvm-svn: 254089
* Let SelectionDAG start to use probability-based interface to add successors.Cong Hou2015-11-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes. 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights. 3. Use new interfaces in all other passes. 4. Remove old interfaces. This the second patch above. In this patch SelectionDAG starts to use probability-based interfaces in MBB to add successors but other MC passes are still using weight-based interfaces. Therefore, we need to maintain correct weight list in MBB even when probability-based interfaces are used. This is done by updating weight list in probability-based interfaces by treating the numerator of probabilities as weights. This change affects many test cases that check successor weight values. I will update those test cases once this patch looks good to you. Differential revision: http://reviews.llvm.org/D14361 llvm-svn: 253965
* Revert "Change memcpy/memset/memmove to have dest and source alignments."Pete Cooper2015-11-192-8/+8
| | | | | | | | | | This reverts commit r253511. This likely broke the bots in http://lab.llvm.org:8011/builders/clang-ppc64-elf-linux2/builds/20202 http://bb.pgr.jp/builders/clang-3stage-i686-linux/builds/3787 llvm-svn: 253543
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