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* [RDF] Remove the map of reaching defs from copy propagationKrzysztof Parzyszek2017-03-101-2/+2
| | | | | | Use Liveness::getNearestAliasedRef to find the reaching def instead. llvm-svn: 297526
* [Hexagon] Fixes to the bitsplit generationKrzysztof Parzyszek2017-03-091-0/+33
| | | | | | | | - Fix the insertion point, which occasionally could have been incorrect. - Avoid creating multiple bitsplits with the same operands, if an old one could be reused. llvm-svn: 297414
* [Hexagon] Propagate zext of i1 into arithmetic code in selection DAGKrzysztof Parzyszek2017-03-093-54/+60
| | | | | | | (op ... (zext i1 c) ...) -> (select c (op ... 1 ...), (op ... 0 ...)) llvm-svn: 297391
* [Hexagon] Use correct offset when extracting from the high wordKrzysztof Parzyszek2017-03-081-0/+23
| | | | | | | | When extracting a bitfield from the high register in a register pair, the final offset should be relative to the high register (for 32-bit extracts). llvm-svn: 297288
* [Hexagon] Check for presence before looking registers up in bit trackerKrzysztof Parzyszek2017-03-071-0/+64
| | | | llvm-svn: 297240
* [Hexagon] Generate bitsplit instructionKrzysztof Parzyszek2017-03-072-0/+52
| | | | llvm-svn: 297239
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-0/+1
| | | | llvm-svn: 297141
* Revert r297039, it's causing some mysterious buildbot failuresKrzysztof Parzyszek2017-03-061-27/+0
| | | | llvm-svn: 297062
* [IfConversion] Only renormalize probabilities if branches are analyzableKrzysztof Parzyszek2017-03-061-0/+36
| | | | | | | | | | | If a block has non-analyzable branches, the listed successors don't need to add up to one. For example, if a block has a conditional tail call, that tail call will not have a corresponding successor in the successor list, but will still be a possible branch. Differential Revision: https://reviews.llvm.org/D30556 llvm-svn: 297054
* [TableGen] Ensure proper ordering of subtarget feature namesKrzysztof Parzyszek2017-03-061-0/+27
| | | | llvm-svn: 297039
* [Hexagon] Early-if-convert branches that may exit the loopKrzysztof Parzyszek2017-03-062-1/+92
| | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033
* [Hexagon] Mark dead defs as <dead> in expand-condsetsKrzysztof Parzyszek2017-03-062-0/+99
| | | | | | | | | The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-061-0/+110
| | | | llvm-svn: 297031
* [Hexagon] Pick the right branch opcode depending on branch probabilitiesKrzysztof Parzyszek2017-03-021-0/+44
| | | | | | | Specifically, pick the opcode with the correct branch prediction, i.e. jump:t or jump:nt. llvm-svn: 296821
* [Hexagon] Skip blocks that define vector predicate registers in early-ifKrzysztof Parzyszek2017-03-021-0/+37
| | | | llvm-svn: 296777
* [Hexagon] Properly handle 'q' constraint in 128-byte vector modeKrzysztof Parzyszek2017-03-021-0/+15
| | | | llvm-svn: 296772
* [Hexagon] Fix lowering of formal arguments of type i1Krzysztof Parzyszek2017-03-011-0/+6
| | | | | | | | | | | On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. llvm-svn: 296645
* [Hexagon] Generate extract instructions more aggressivelyKrzysztof Parzyszek2017-02-284-3/+81
| | | | llvm-svn: 296537
* [Hexagon] Fix instruction selection for sign-extending i1 to i64Krzysztof Parzyszek2017-02-281-0/+22
| | | | llvm-svn: 296532
* [Hexagon] Undo shift folding where it could simplify addressing modeKrzysztof Parzyszek2017-02-241-0/+59
| | | | | | | | | | | | For example, avoid (single shift): r0 = and(##536870908,lsr(r0,#3)) r0 = memw(r1+r0<<#0) in favor of (two shifts): r0 = lsr(r0,#5) r0 = memw(r1+r0<<#2) llvm-svn: 296196
* [DAGCombiner] add missing folds for scalar select of {-1,0,1}Sanjay Patel2017-02-242-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | The motivation for filling out these select-of-constants cases goes back to D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to: https://reviews.llvm.org/rL75531 https://reviews.llvm.org/rL159230 The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today: https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151 As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization: 1. Have DAGCombiner convert any select of constants into ext/add/not ops. 2 Have InstCombine canonicalize in the other direction (create more selects). Differential Revision: https://reviews.llvm.org/D30180 llvm-svn: 296137
* [Hexagon] Handle saturations in Hexagon bit trackerKrzysztof Parzyszek2017-02-231-0/+57
| | | | llvm-svn: 296026
* [Hexagon] Avoid IMPLICIT_DEFs as new-value producersKrzysztof Parzyszek2017-02-231-0/+79
| | | | llvm-svn: 295997
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-232-36/+135
| | | | llvm-svn: 295981
* [Hexagon] Implement @llvm.readcyclecounter()Krzysztof Parzyszek2017-02-221-0/+10
| | | | llvm-svn: 295892
* [Hexagon] Add intrinsics for masked vector storesKrzysztof Parzyszek2017-02-222-0/+82
| | | | | | Patch by Harsha Jagasia. llvm-svn: 295879
* Bring back 2>&1 redirection for this testMatthias Braun2017-02-221-1/+1
| | | | llvm-svn: 295864
* MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun2017-02-221-1/+1
| | | | | | | llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-172-3/+2
| | | | | | Reapply r295371 with a fix for the Windows bot failures. llvm-svn: 295504
* Revert "[Hexagon] Start using regmasks on calls"Rafael Espindola2017-02-172-2/+3
| | | | | | | | | | This reverts commit r295371. It broke windows bots: http://bb.pgr.jp/builders/ninja-clang-i686-msc19-R/builds/11402/steps/test-llvm/logs/stdio llvm-svn: 295402
* [Hexagon] Start using regmasks on callsKrzysztof Parzyszek2017-02-162-3/+2
| | | | | | All the cool targets are doing it... llvm-svn: 295371
* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-1091-934/+934
| | | | llvm-svn: 294753
* [Hexagon] Remove encoding bits from mapped instructionsKrzysztof Parzyszek2017-02-072-0/+172
| | | | | | | | | | - Map A2_zxtb to A2_andir. - Map PS_call_nr J2_call. - Map A2_tfr[t|f][new] to A2_padd[t|f][new]. Patch by Colin LeMahieu. llvm-svn: 294320
* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-064-12/+12
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [Hexagon] Fix insertBranch for loops with multiple ENDLOOP instructionsKrzysztof Parzyszek2017-02-021-0/+79
| | | | llvm-svn: 293925
* [Hexagon] Add Hexagon-specific loop idiom recognition passKrzysztof Parzyszek2017-01-265-0/+175
| | | | llvm-svn: 293213
* Treat segment [B, E) as not overlapping block with boundaries [A, B)Krzysztof Parzyszek2017-01-181-0/+143
| | | | llvm-svn: 292446
* [Hexagon] Remove dead defs from the live set when expanding wstoresKrzysztof Parzyszek2017-01-181-0/+216
| | | | llvm-svn: 292445
* Fix two bugs in the pipeliner in renaming phis in the prolog and epilogKrzysztof Parzyszek2016-12-222-0/+153
| | | | | | | | | | | | | | | When the pipeliner is renaming phi values, it may need to iterate through the phi operands to check for other phis. However, the pipeliner should stop once it reaches a phi that is outside the pipelined loop. Also, when the generateExistingPhis code is unable to reuse an existing phi, the default code that computes the PhiOp2 is only to be used when the pipeliner is generating the kernel. Otherwise, the phi may be a value computed earlier in the same epilog. Patch by Brendon Cahoon. llvm-svn: 290355
* Move .mir tests to appropriate directoriesMatthias Braun2016-12-091-0/+34
| | | | | | | | | | | test/CodeGen/MIR should contain tests that intent to test the MIR printing or parsing. Tests that test something else should be in test/CodeGen/TargetName even when they are written in .mir. As a rule of thumb, only tests using "llc -run-pass none" should be in test/CodeGen/MIR. llvm-svn: 289254
* [Hexagon] Remove unsafe load instructions that affect Stack Slot ColoringSumanth Gundapaneni2016-11-141-0/+131
| | | | | | | | | | | | | | | | | The Stack slot coloring pass removes a store that is followed by a load that deal with the same stack slot. The function isLoadFromStackSlot is supposed to consider the loads that have no side-effects. This patch fixed the issue by removing the unsafe loads from this function Eg: %vreg0<def> = L2_loadruh_io <fi#15>, 0 S2_storeri_io <fi#15>, 0, %vreg0 In this case, we load an unsigned extended half word and store this in to the same stack slot. The Stack slot coloring pass considers safe to remove the store. This patch marked all the non-vector byte and half word loads as unsafe. llvm-svn: 286843
* [Hexagon] Separate Hexagon subreg indices for different register classesKrzysztof Parzyszek2016-11-092-14/+14
| | | | | | | | | | | For pairs of 32-bit registers: isub_lo, isub_hi. For pairs of vector registers: vsub_lo, vsub_hi. Add generic subreg indices: ps_sub_lo, ps_sub_hi, and a function HexagonRegisterInfo::getHexagonSubRegIndex(RegClass, GenericSubreg) that returns the appropriate subreg index for RegClass. llvm-svn: 286377
* [Hexagon] Eliminate Insert4 pseudo-instruction, use combines insteadKrzysztof Parzyszek2016-11-091-5/+5
| | | | llvm-svn: 286368
* [Hexagon] Account for <def,read-undef> when validating moves for predicationKrzysztof Parzyszek2016-11-041-0/+41
| | | | llvm-svn: 286009
* [Hexagon] Remove registers coalesced in expand-condsets from live intervalsKrzysztof Parzyszek2016-11-021-0/+49
| | | | llvm-svn: 285846
* [Hexagon] Don't expand mux instructions with both sources identicalKrzysztof Parzyszek2016-10-311-0/+32
| | | | llvm-svn: 285588
* Handle non-~0 lane masks on live-in registers in LivePhysRegsKrzysztof Parzyszek2016-10-281-0/+55
| | | | | | | | | | | | | | | | | When LivePhysRegs adds live-in registers, it recognizes ~0 as a special lane mask indicating the entire register. If the lane mask is not ~0, it will only add the subregisters that overlap the specified lane mask. The problem is that if a live-in register does not have subregisters, and the lane mask is not ~0, it will not be added to the live set. (The given lane mask may simply be the lane mask of its register class.) If a register does not have subregisters, add it to the live set if the lane mask is non-zero. Differential Revision: https://reviews.llvm.org/D26094 llvm-svn: 285440
* [Hexagon] Maintain kill flags through splitting in expand-condsetsKrzysztof Parzyszek2016-10-281-0/+78
| | | | | | | Do not use LiveIntervals to recalculate kills, because that cannot be done accurately without implicit uses on predicated instructions. llvm-svn: 285409
* [Hexagon] Do not expand ISD::SELECT for HVX vectorsKrzysztof Parzyszek2016-10-271-0/+69
| | | | llvm-svn: 285297
* [Hexagon] Handle spills of partially defined double vector registersKrzysztof Parzyszek2016-10-211-0/+95
| | | | | | | | | | | | After register allocation it is possible to have a spill of a register that is only partially defined. That in itself it fine, but creates a problem for double vector registers. Stores of such registers are pseudo instructions that are expanded into pairs of individual vector stores, and in case of a partially defined source, one of the stores may use an entirely undefined register. To avoid this, track the defined parts and only generate actual stores for those. llvm-svn: 284841
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