| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Reorganize and update instruction patterns | Krzysztof Parzyszek | 2017-10-20 | 1 | -1/+1 |
| * | [Hexagon] New HVX target features. | Sumanth Gundapaneni | 2017-10-18 | 1 | -1/+1 |
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -6/+6 |
| * | [Hexagon] Add SDAG preprocessing step to expose shifted addressing modes | Krzysztof Parzyszek | 2016-06-22 | 1 | -0/+50 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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