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* [Hexagon] Adding gp+ to the syntax of gp-relative instructionsKrzysztof Parzyszek2017-02-061-3/+3
| | | | | | Patch by Colin LeMahieu. llvm-svn: 294258
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-211-4/+4
| | | | llvm-svn: 267034
* [Hexagon] Fixing load instruction parsing and reenabling tests.Colin LeMahieu2015-11-101-1/+0
| | | | llvm-svn: 252555
* [Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction ↵Colin LeMahieu2015-11-091-0/+1
| | | | | | parsing tests. General updating of the code emission. llvm-svn: 252443
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* Porting Hexagon MI Scheduler to the new API.Sergei Larin2012-09-041-1/+1
| | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137
* Enable all Hexagon tests.Sirish Pande2012-05-151-5/+4
| | | | llvm-svn: 156824
* Disable Hexagon test temporarily.Sirish Pande2012-04-121-1/+2
| | | | | | | | | | | | | There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617
* VLIW specific scheduler framework that utilizes deterministic finite ↵Andrew Trick2012-02-011-2/+2
| | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547
* Hexagon: Fix a nasty order-of-initialization bug.Benjamin Kramer2011-12-161-2/+1
| | | | | | Reenable the tests. llvm-svn: 146750
* Temporarily disable Hexagon tests. They are failing on OS XTony Linthicum2011-12-131-1/+2
| | | | llvm-svn: 146455
* Hexagon backend supportTony Linthicum2011-12-121-0/+20
llvm-svn: 146412
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