| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Reorganize and update instruction patterns | Krzysztof Parzyszek | 2017-10-20 | 1 | -1/+1 |
| | | | | | llvm-svn: 316228 | ||||
| * | Add address space mangling to lifetime intrinsics | Matt Arsenault | 2017-04-10 | 1 | -6/+6 |
| | | | | | | | In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876 | ||||
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -2/+2 |
| | | | | | llvm-svn: 294753 | ||||
| * | [LSR] Don't try and create post-inc expressions on non-rotated loops | James Molloy | 2016-08-15 | 1 | -2/+0 |
| | | | | | | | | | | | | | | | | If a loop is not rotated (for example when optimizing for size), the latch is not the backedge. If we promote an expression to post-inc form, we not only increase register pressure and add a COPY for that IV expression but for all IVs! Motivating testcase: void f(float *a, float *b, float *c, int n) { while (n-- > 0) *c++ = *a++ + *b++; } It's imperative that the pointer increments be located in the latch block and not the header block; if not, we cannot use post-increment loads and stores and we have to keep both the post-inc and pre-inc values around until the end of the latch which bloats register usage. llvm-svn: 278658 | ||||
| * | [Hexagon] Generate loop1 instruction for nested loops | Brendon Cahoon | 2015-05-13 | 1 | -0/+68 |
| loop1 is for the outer loop and loop0 is for the inner loop. Differential Revision: http://reviews.llvm.org/D9680 llvm-svn: 237266 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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