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path: root/llvm/test/CodeGen/Hexagon/extload-combine.ll
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* [Hexagon] Replace instruction definitions with auto-generated onesKrzysztof Parzyszek2017-02-101-9/+9
| | | | llvm-svn: 294753
* [Hexagon] Expand handling of the small-data/bss sectionKrzysztof Parzyszek2016-04-211-1/+1
| | | | llvm-svn: 267034
* [Hexagon] Split double registersKrzysztof Parzyszek2015-10-161-1/+1
| | | | llvm-svn: 250549
* [opaque pointer type] Add textual IR support for explicit type parameter to ↵David Blaikie2015-02-271-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
* Hexagon: Add patterns to generate 'combine' instructions.Jyotsna Verma2013-05-141-0/+80
llvm-svn: 181805
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