| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -10/+10 |
| * | [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-30 | 1 | -2/+2 |
| * | MIR: Print the register class or bank in vreg defs | Justin Bogner | 2017-10-24 | 1 | -2/+2 |
| * | Bring back 2>&1 redirection for this test | Matthias Braun | 2017-02-22 | 1 | -1/+1 |
| * | MIRTests: Remove unnecessary 2>&1 redirection | Matthias Braun | 2017-02-22 | 1 | -1/+1 |
| * | [Hexagon] Remove registers coalesced in expand-condsets from live intervals | Krzysztof Parzyszek | 2016-11-02 | 1 | -0/+49 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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