| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Update more testcases | Krzysztof Parzyszek | 2018-03-06 | 1 | -1/+1 |
| | | | | | llvm-svn: 326830 | ||||
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -1/+1 |
| | | | | | llvm-svn: 294753 | ||||
| * | [Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors | Krzysztof Parzyszek | 2016-08-03 | 1 | -1/+1 |
| | | | | | llvm-svn: 277626 | ||||
| * | [Hexagon] Split double registers | Krzysztof Parzyszek | 2015-10-16 | 1 | -1/+1 |
| | | | | | llvm-svn: 250549 | ||||
| * | [opaque pointer type] Add textual IR support for explicit type parameter to ↵ | David Blaikie | 2015-02-27 | 1 | -2/+2 |
| | | | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 | ||||
| * | Enable all Hexagon tests. | Sirish Pande | 2012-05-15 | 1 | -2/+1 |
| | | | | | llvm-svn: 156824 | ||||
| * | Disable Hexagon test temporarily. | Sirish Pande | 2012-04-12 | 1 | -1/+2 |
| | | | | | | | | | | | | | | There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617 | ||||
| * | Hexagon: Fix a nasty order-of-initialization bug. | Benjamin Kramer | 2011-12-16 | 1 | -2/+1 |
| | | | | | | | Reenable the tests. llvm-svn: 146750 | ||||
| * | Temporarily disable Hexagon tests. They are failing on OS X | Tony Linthicum | 2011-12-13 | 1 | -1/+2 |
| | | | | | llvm-svn: 146455 | ||||
| * | Hexagon backend support | Tony Linthicum | 2011-12-12 | 1 | -0/+17 |
| llvm-svn: 146412 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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