bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[DAGCombine] Improve Load-Store Forwarding	Nirav Dave	2018-10-10	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
*	[Hexagon] Update more testcases	Krzysztof Parzyszek	2018-03-06	1	-1/+1
\| \| \| \|	llvm-svn: 326830
*	[Hexagon] Replace instruction definitions with auto-generated ones	Krzysztof Parzyszek	2017-02-10	1	-15/+15
\| \| \| \|	llvm-svn: 294753
*	[Hexagon] Improve patterns with stack-based addressing	Krzysztof Parzyszek	2016-07-15	1	-1/+16
\| \| \| \| \| \| \| \| \|	- Treat bitwise OR with a frame index as an ADD wherever possible, fold it into addressing mode. - Extend patterns for memops to allow memops with frame indexes as address operands. llvm-svn: 275569
*	[Hexagon] Bit-based instruction simplification	Krzysztof Parzyszek	2015-10-20	1	-1/+1
\| \| \| \| \| \| \|	Analyze bit patterns of operands and values of instructions to perform various simplifications, dead/redundant code elimination, etc. llvm-svn: 250868
*	Missed testcase for r232577	Krzysztof Parzyszek	2015-03-18	1	-0/+160
	llvm-svn: 232578