Commit message (Expand) | Author | Age | Files | Lines | |
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* | [Hexagon] Update more testcases | Krzysztof Parzyszek | 2018-03-06 | 1 | -38/+34 |
* | [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output | Francis Visoiu Mistrih | 2017-11-30 | 1 | -4/+4 |
* | [Hexagon] Intrinsics for circular and bit-reversed loads and stores | Krzysztof Parzyszek | 2015-03-18 | 1 | -0/+255 |