| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Add support to handle bit-reverse load intrinsics | Krzysztof Parzyszek | 2018-03-29 | 1 | -10/+10 |
| | | | | | | | Patch by Sumanth Gundapaneni. llvm-svn: 328774 | ||||
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -5/+5 |
| | | | | | llvm-svn: 294753 | ||||
| * | [Hexagon] Eliminate pseudo instructions for circ/brev loads and stores | Krzysztof Parzyszek | 2016-02-12 | 1 | -14/+5 |
| | | | | | | | | | | We can generate the actual instructions from the intrinsics without the need for pseudo-instructions. Also, since the intrinsics have a side- effect in a form of a store, attempt to optimize away loads from the store location. llvm-svn: 260690 | ||||
| * | [Hexagon] Intrinsics for circular and bit-reversed loads and stores | Krzysztof Parzyszek | 2015-03-18 | 1 | -0/+112 |
| llvm-svn: 232645 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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