| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Update more testcases | Krzysztof Parzyszek | 2018-03-06 | 1 | -1/+1 |
| | | | | | llvm-svn: 326830 | ||||
| * | [Hexagon] Reorganize and update instruction patterns | Krzysztof Parzyszek | 2017-10-20 | 1 | -2/+1 |
| | | | | | llvm-svn: 316228 | ||||
| * | [Hexagon] Early-if-convert branches that may exit the loop | Krzysztof Parzyszek | 2017-03-06 | 1 | -1/+1 |
| | | | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033 | ||||
| * | [Hexagon] Mark PS_jumpret as pseudo-instruction, expand it into J2_jumpr | Krzysztof Parzyszek | 2016-08-19 | 1 | -4/+3 |
| | | | | | llvm-svn: 279241 | ||||
| * | [Hexagon] Treat all conditional branches as predicted (not-taken by default) | Krzysztof Parzyszek | 2016-05-09 | 1 | -1/+1 |
| | | | | | llvm-svn: 268946 | ||||
| * | [Hexagon] Use A2_tfrsi for constant pool and jump table addresses | Krzysztof Parzyszek | 2015-04-22 | 1 | -2/+3 |
| | | | | | llvm-svn: 235535 | ||||
| * | [opaque pointer type] Add textual IR support for explicit type parameter to ↵ | David Blaikie | 2015-02-27 | 1 | -7/+7 |
| | | | | | | | | | | | | | | | | | | | | | | | | | load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794 | ||||
| * | [Hexagon] Adding reg-reg indexed load forms. | Colin LeMahieu | 2014-12-30 | 1 | -1/+1 |
| | | | | | llvm-svn: 224997 | ||||
| * | Hexagon: Add support to lower block address. | Jyotsna Verma | 2013-03-07 | 1 | -0/+64 |
| | | | | | llvm-svn: 176637 | ||||
| * | reverting patch 176508. | Jyotsna Verma | 2013-03-05 | 1 | -64/+0 |
| | | | | | llvm-svn: 176513 | ||||
| * | Hexagon: Add support for lowering block address. | Jyotsna Verma | 2013-03-05 | 1 | -0/+64 |
| llvm-svn: 176508 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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