| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | [Hexagon] Add patterns for sext_inreg of HVX vector types | Krzysztof Parzyszek | 2018-01-05 | 1 | -0/+54 | |
| | | | | | llvm-svn: 321894 | |||||
| * | [Hexagon] Fix generation of vector sign extensions | Krzysztof Parzyszek | 2018-01-02 | 2 | -16/+48 | |
| | | | | | llvm-svn: 321650 | |||||
| * | [Hexagon] Allow construction of HVX vector predicates | Krzysztof Parzyszek | 2017-12-20 | 2 | -0/+37 | |
| | | | | | | | Handle BUILD_VECTOR of boolean values. llvm-svn: 321220 | |||||
| * | [Hexagon] Cache loads to select to avoid traversing mutating DAG | Krzysztof Parzyszek | 2017-12-18 | 1 | -0/+32 | |
| | | | | | llvm-svn: 321034 | |||||
| * | [Hexagon] Generate HVX code for vector sign-, zero- and any-extends | Krzysztof Parzyszek | 2017-12-18 | 3 | -0/+130 | |
| | | | | | | | Implement any-extend as zero-extend. llvm-svn: 321004 | |||||
| * | [Hexagon] Handle concat_vectors of all allowed HVX types | Krzysztof Parzyszek | 2017-12-15 | 3 | -0/+82 | |
| | | | | | llvm-svn: 320865 | |||||
| * | [Hexagon] Generate HVX code for comparisons and selects | Krzysztof Parzyszek | 2017-12-14 | 2 | -0/+588 | |
| | | | | | llvm-svn: 320744 | |||||
| * | [Hexagon] Relax some checks in testcases, NFC | Krzysztof Parzyszek | 2017-12-12 | 2 | -95/+95 | |
| | | | | | llvm-svn: 320529 | |||||
| * | [Hexagon] Better detection of identity and undef masks in shuffles | Krzysztof Parzyszek | 2017-12-12 | 1 | -6/+4 | |
| | | | | | llvm-svn: 320523 | |||||
| * | [Hexagon] Fix wrong order of operands for vmux | Krzysztof Parzyszek | 2017-12-12 | 1 | -0/+15 | |
| | | | | | | | | | | | | | Shuffle generation uses vmux to collapse vectors resulting from two individual shuffles into one. The indexes of the elements selected from the first operand were indicated by 0xFF in the constant vector used in the compare instruction, but the compare (veqb) set the bits corresponding to the 0x00 elements, thus inverting the selection. Reverse the order of operands to vmux to get the correct output. llvm-svn: 320516 | |||||
| * | [Hexagon] Crash in instruction selection for insert_vector_elt for HVX | Krzysztof Parzyszek | 2017-12-11 | 1 | -0/+23 | |
| | | | | | | | | | A wrong type was passed to insertVector, causing an out-of-bounds value to be added an an operand to HexagonISD::INSERT. This later failed in instruction selection. llvm-svn: 320369 | |||||
| * | [Hexagon] Generate HVX code for basic arithmetic operations | Krzysztof Parzyszek | 2017-12-07 | 1 | -0/+278 | |
| | | | | | | | Handle and, or, xor, add, sub, mul for vectors of i8, i16, and i32. llvm-svn: 320063 | |||||
| * | [Hexagon] Recognize vdealb, vdealh, vshuffb and vshuffh specifically | Krzysztof Parzyszek | 2017-12-06 | 1 | -0/+62 | |
| | | | | | llvm-svn: 319978 | |||||
| * | [Hexagon] Handle perfect shuffles on single vectors | Krzysztof Parzyszek | 2017-12-06 | 1 | -0/+20 | |
| | | | | | llvm-svn: 319965 | |||||
| * | [Hexagon] Generate HVX code for vector construction and access | Krzysztof Parzyszek | 2017-12-06 | 15 | -0/+5865 | |
| Support for: - build vector, - extract vector element, subvector, - insert vector element, subvector, - shuffle. llvm-svn: 319901 | ||||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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