| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [DAGCombiner] allow hoisting vector bitwise logic ahead of truncates | Sanjay Patel | 2018-12-16 | 1 | -9/+9 |
| * | [Hexagon] Add patterns for accumulating HVX compares | Krzysztof Parzyszek | 2018-05-22 | 1 | -36/+29 |
| * | [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patterns | Krzysztof Parzyszek | 2018-05-16 | 1 | -0/+102 |
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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