| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Update more testcases | Krzysztof Parzyszek | 2018-03-06 | 1 | -3/+3 |
| | | | | | llvm-svn: 326830 | ||||
| * | [Hexagon] Replace instruction definitions with auto-generated ones | Krzysztof Parzyszek | 2017-02-10 | 1 | -4/+4 |
| | | | | | llvm-svn: 294753 | ||||
| * | [Hexagon] Adding some codegen tests and updating some to match spec. | Colin LeMahieu | 2015-06-13 | 1 | -1/+1 |
| | | | | | llvm-svn: 239690 | ||||
| * | [Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing. | Colin LeMahieu | 2015-06-05 | 1 | -4/+4 |
| | | | | | llvm-svn: 239161 | ||||
| * | Shouldn't be XFAIL'ed. | Colin LeMahieu | 2015-06-04 | 1 | -1/+0 |
| | | | | | llvm-svn: 239103 | ||||
| * | Revert r239095 incorrect test tree. | Colin LeMahieu | 2015-06-04 | 1 | -0/+1 |
| | | | | | llvm-svn: 239102 | ||||
| * | Hexagon: Pass to replace tranfer/copy instructions into combine instruction | Jyotsna Verma | 2013-05-14 | 1 | -6/+3 |
| | | | | | | | where possible. llvm-svn: 181817 | ||||
| * | Hexagon: Add encoding bits to the TFR64 instructions. | Jyotsna Verma | 2013-03-05 | 1 | -2/+2 |
| | | | | | | | Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions. llvm-svn: 176499 | ||||
| * | Use multiclass to define store instructions with base+immediate offset | Jyotsna Verma | 2012-12-05 | 1 | -2/+1 |
| | | | | | | | addressing mode and immediate stored value. llvm-svn: 169408 | ||||
| * | Porting Hexagon MI Scheduler to the new API. | Sergei Larin | 2012-09-04 | 1 | -2/+2 |
| | | | | | | | | Change current Hexagon MI scheduler to use new converging scheduler. Integrates DFA resource model into it. llvm-svn: 163137 | ||||
| * | Enable all Hexagon tests. | Sirish Pande | 2012-05-15 | 1 | -2/+1 |
| | | | | | llvm-svn: 156824 | ||||
| * | Disable Hexagon test temporarily. | Sirish Pande | 2012-04-12 | 1 | -1/+2 |
| | | | | | | | | | | | | | | There is an assert at line 558 in ScheduleDAGInstrs::buildSchedGraph(AliasAnalysis *AA). This assert needs to addressed for post RA scheduler. Until that assert is addressed, any passes that uses post ra scheduler will fail. So, I am temporarily disabling the hexagon tests until that fix is in. The assert is as follows: assert(!MI->isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); llvm-svn: 154617 | ||||
| * | VLIW specific scheduler framework that utilizes deterministic finite ↵ | Andrew Trick | 2012-02-01 | 1 | -1/+1 |
| | | | | | | | | | | | automaton (DFA). This new scheduler plugs into the existing selection DAG scheduling framework. It is a top-down critical path scheduler that tracks register pressure and uses a DFA for pipeline modeling. Patch by Sergei Larin! llvm-svn: 149547 | ||||
| * | Hexagon: Fix a nasty order-of-initialization bug. | Benjamin Kramer | 2011-12-16 | 1 | -2/+1 |
| | | | | | | | Reenable the tests. llvm-svn: 146750 | ||||
| * | Temporarily disable Hexagon tests. They are failing on OS X | Tony Linthicum | 2011-12-13 | 1 | -1/+2 |
| | | | | | llvm-svn: 146455 | ||||
| * | Hexagon backend support | Tony Linthicum | 2011-12-12 | 1 | -0/+18 |
| llvm-svn: 146412 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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