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* Remove the CellSPU port.Eric Christopher2012-11-141-348/+0
| | | | | | Approved by Chris Lattner. llvm-svn: 167984
* Convert all tests using TCL-style quoting to use shell-style quoting.Chandler Carruth2012-07-021-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | This was done through the aid of a terrible Perl creation. I will not paste any of the horrors here. Suffice to say, it require multiple staged rounds of replacements, state carried between, and a few nested-construct-parsing hacks that I'm not proud of. It happens, by luck, to be able to deal with all the TCL-quoting patterns in evidence in the LLVM test suite. If anyone is maintaining large out-of-tree test trees, feel free to poke me and I'll send you the steps I used to convert things, as well as answer any painful questions etc. IRC works best for this type of thing I find. Once converted, switch the LLVM lit config to use ShTests the same as Clang. In addition to being able to delete large amounts of Python code from 'lit', this will also simplify the entire test suite and some of lit's architecture. Finally, the test suite runs 33% faster on Linux now. ;] For my 16-hardware-thread (2x 4-core xeon e5520): 36s -> 24s llvm-svn: 159525
* Enable element promotion type legalization by deafault.Nadav Rotem2011-10-161-4/+4
| | | | | | Changed tests which assumed that vectors are legalized by widening them. llvm-svn: 142152
* Fix a bug in LowerV2I64Splat, which generated a BUILD_VECTOR for which there wasNadav Rotem2011-10-161-0/+4
| | | | | | no pattern. llvm-svn: 142130
* manually upgrade a bunch of tests to modern syntax, and remove some thatChris Lattner2011-06-171-24/+24
| | | | | | are either unreduced or only test old syntax. llvm-svn: 133228
* Allow vector shifts (shl,lshr,ashr) on SPU.Kalle Raiskila2011-03-041-6/+55
| | | | | | | | | There was a previous implementation with patterns that would have matched e.g. shl <v4i32> <i32>, but this is not valid LLVM IR so they never were selected. llvm-svn: 126998
* fix visitShift to properly zero extend the shift amount if the provided operandChris Lattner2011-02-131-1/+1
| | | | | | | is narrower than the shift register. Doing an anyext provides undefined bits in the top part of the register. llvm-svn: 125457
* Handle lshr for i128 correctly on SPU also when Kalle Raiskila2010-11-291-2/+14
| | | | | | shiftamount > 7. llvm-svn: 120288
* Convert more tests to avoid llvm-as.Dan Gohman2009-09-111-1/+1
| | | | llvm-svn: 81545
* Revert 67132. This is breaking some objective-c apps.Evan Cheng2009-03-251-0/+2
| | | | | | Also fixes SDISel so it *does not* force promote return value if the function is not marked signext / zeroext. llvm-svn: 67701
* Don't force promotion of return arguments on the callee.Rafael Espindola2009-03-171-2/+0
| | | | | | | Some architectures (like x86) don't require it. This fixes bug 3779. llvm-svn: 67132
* CellSPU:Scott Michel2009-01-261-0/+6
| | | | | | | | | | | | | | | | - Rename fcmp.ll test to fcmp32.ll, start adding new double tests to fcmp64.ll - Fix select_bits.ll test - Capitulate to the DAGCombiner and move i64 constant loads to instruction selection (SPUISelDAGtoDAG.cpp). <rant>DAGCombiner will insert all kinds of 64-bit optimizations after operation legalization occurs and now we have to do most of the work that instruction selection should be doing twice (once to determine if v2i64 build_vector can be handled by SelectCode(), which then runs all of the predicates a second time to select the necessary instructions.) But, CellSPU is a good citizen.</rant> llvm-svn: 62990
* Don't rely on grep -w working.Duncan Sands2009-01-211-16/+16
| | | | llvm-svn: 62682
* Fix off-by-one error in traversing an array; this fixes a test.Misha Brukman2009-01-071-2/+0
| | | | | | The error was reported by gcc-4.3.0 during compilation. llvm-svn: 61896
* This is not failing on Darwin for some reason. XFAIL for other platforms.Bill Wendling2008-12-311-1/+1
| | | | llvm-svn: 61533
* XFAIL this for now until I can figure out what's going on.Scott Michel2008-12-311-1/+3
| | | | llvm-svn: 61512
* Fix test erratum (which is wierd: works locally for me?)Scott Michel2008-12-301-1/+1
| | | | llvm-svn: 61511
* - Start moving target-dependent nodes that could be represented by anScott Michel2008-12-301-6/+71
| | | | | | | | | | | | | instruction sequence and cannot ordinarily be simplified by DAGcombine into the various target description files or SPUDAGToDAGISel.cpp. This makes some 64-bit operations legal. - Eliminate target-dependent ISD enums. - Update tests. llvm-svn: 61508
* - Expand tabs to spaces.Scott Michel2008-03-051-72/+72
| | | | | | | | - select_bits.ll now fully functional now that PR1993 is closed. It was previously broken by refactoring in SPUInstrInfo.td and using multiclasses. - Same for eqv.ll llvm-svn: 47972
* More CellSPU refinement and progress:Scott Michel2008-01-111-0/+2
| | | | | | | | | | | | | | | | | | | | - Cleaned up custom load/store logic, common code is now shared [see note below], cleaned up address modes - More test cases: various intrinsics, structure element access (load/store test), updated target data strings, indirect function calls. Note: This patch contains a refactoring of the LoadSDNode and StoreSDNode structures: they now share a common base class, LSBaseSDNode, that provides an interface to their common functionality. There is some hackery to access the proper operand depending on the derived class; otherwise, to do a proper job would require finding and rearranging the SDOperands sent to StoreSDNode's constructor. The current refactor errs on the side of being conservatively and backwardly compatible while providing functionality that reduces redundant code for targets where loads and stores are custom-lowered. llvm-svn: 45851
* More working CellSPU test cases:Scott Michel2007-12-191-0/+210
- call.ll: Function call - ctpop.ll: Count population - dp_farith.ll: DP arithmetic - eqv.ll: Equivalence primitives - fcmp.ll: SP comparisons - fdiv.ll: SP division - fneg-fabs.ll: SP negation, aboslute value - int2fp.ll: Integer -> SP conversion - rotate_ops.ll: Rotation primitives - select_bits.ll: (a & c) | (b & ~c) bit selection - shift_ops.ll: Shift primitives - sp_farith.ll: SP arithmentic llvm-svn: 45217
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