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* Handle perfect shuffle case that generates a vrev for vectors of floats.Tanya Lattner2011-05-181-0/+15
| | | | | | Add test case. llvm-svn: 131582
* In r131488 I misunderstood how VREV works. It splits the vector in half and ↵Tanya Lattner2011-05-181-3/+2
| | | | | | | | splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. llvm-svn: 131529
* vrev is incorrectly defined in the perfect shuffle table. The ordering is ↵Tanya Lattner2011-05-171-0/+17
| | | | | | backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. llvm-svn: 131488
* Teach LiveInterval::isZeroLength about null SlotIndexes.Jakob Stoklund Olesen2011-05-161-4/+4
| | | | | | | | | | | | When instructions are deleted, they leave tombstone SlotIndex entries. The isZeroLength method should ignore these null indexes. This causes RABasic to sometimes spill a callee-saved register in the abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing register allocation according to spill weight can cause more registers to be used. llvm-svn: 131436
* Correction. Use explicit target triple in the test.Galina Kistanova2011-05-121-1/+1
| | | | llvm-svn: 131252
* Fixes a bug in the DAGCombiner. LoadSDNodes have two values (data, chain).Nadav Rotem2011-05-111-4/+8
| | | | | | | | If there is a store after the load node, then there is a chain, which means that there is another user. Thus, asking hasOneUser would fail. Instead we ask hasNUsesOfValue on the 'data' value. llvm-svn: 131183
* Produce a __debug_frame section on darwin ARM when appropriate.Rafael Espindola2011-05-101-2/+2
| | | | llvm-svn: 131151
* Give this test an explicit register allocator, so that it can work even ifDan Gohman2011-05-041-1/+1
| | | | | | the default register allocator is changed. llvm-svn: 130883
* SjLj EH could produce a machine basic block that legitimately has more than oneBill Wendling2011-05-041-0/+93
| | | | | | | | | | | | | landing pad as its successor. SjLj exception handling jumps to the correct landing pad via a switch statement that's generated right before code-gen. Loosen the constraint in the machine instruction verifier to allow for this. Note, this isn't the most rigorous check since we cannot determine where that switch statement came from. But it's marginally better than turning this check off when SjLj exceptions are used. <rdar://problem/9187612> llvm-svn: 130881
* This test fails on ARM. The test shouldn't explicitly specify alignment (and ↵Galina Kistanova2011-05-041-4/+4
| | | | | | alignment 4 is wrong) and requires hard-float. llvm-svn: 130875
* Do not emit location expression size twice.Devang Patel2011-05-041-0/+59
| | | | llvm-svn: 130854
* Fix a bunch of ARM tests to be register allocation independent.Jakob Stoklund Olesen2011-05-038-30/+30
| | | | llvm-svn: 130800
* Make the test less likely to fail with minor changes.Evan Cheng2011-05-031-1/+1
| | | | llvm-svn: 130778
* Remove test for iOS divmod function, since that is disabled for now.Bob Wilson2011-05-031-58/+0
| | | | llvm-svn: 130769
* Add a few ARM coprocessor intrinsics. Testcases includedBruno Cardoso Lopes2011-05-031-0/+39
| | | | llvm-svn: 130763
* Add an unfolded offset field to LSR's Formula record. This is used toDan Gohman2011-05-031-0/+80
| | | | | | | | model constants which can be added to base registers via add-immediate instructions which don't require an additional register to materialize the immediate. llvm-svn: 130743
* Weekly fix of register allocation dependent unit tests.Jakob Stoklund Olesen2011-04-305-22/+29
| | | | llvm-svn: 130567
* Make FastEmit_ri_ try a bit harder to succeed for supported operations; ↵Eli Friedman2011-04-291-2/+10
| | | | | | FastEmit_i can fail for non-Thumb2 ARM. Makes ARMSimplifyAddress work correctly, and reduces the number of fast-isel bailouts on non-Thumb ARM. llvm-svn: 130560
* Switch to ImmLeaf (which can be used by FastISel) for a few more common ↵Eli Friedman2011-04-291-5/+29
| | | | | | ARM/Thumb2 patterns. llvm-svn: 130552
* Fix run-line, again. :(Eli Friedman2011-04-291-1/+1
| | | | llvm-svn: 130540
* Re-committing r130454, which does not in fact break anything.Eli Friedman2011-04-291-0/+11
| | | | | | | Fix a rather obscure crash caused by ARM fast-isel generating code which redefines a register. rdar://problem/9338332 . llvm-svn: 130539
* Add trunc->branch support, this won't help with clang's i8->i1 truncationsEric Christopher2011-04-291-1/+16
| | | | | | for bools, but is a start. llvm-svn: 130534
* Revert r130454; apparently this doesn't actually work.Eli Friedman2011-04-281-11/+0
| | | | llvm-svn: 130462
* Fix runline.Eli Friedman2011-04-281-1/+1
| | | | llvm-svn: 130455
* Fix a rather obscure crash caused by ARM fast-isel generating code which ↵Eli Friedman2011-04-281-0/+11
| | | | | | | | redefines a register. rdar://problem/9338332 . llvm-svn: 130454
* Teach dwarf writer to handle complex address expression for .debug_loc entries.Devang Patel2011-04-281-2/+2
| | | | | | | This fixes clang generated blocks' variables' debug info. Radar 9279956. llvm-svn: 130373
* If converter was being too cute. It look for root BBs (which don't haveEvan Cheng2011-04-271-0/+59
| | | | | | | | | | successors) and use inverse depth first search to traverse the BBs. However that doesn't work when the CFG has infinite loops. Simply do a linear traversal of all BBs work just fine. rdar://9344645 llvm-svn: 130324
* Also add <imp-def> operands for defined and dead super-registers when rewriting.Jakob Stoklund Olesen2011-04-271-1/+24
| | | | | | | We cannot rely on the <imp-def> operands added by LiveIntervals in all cases as demonstrated by the test case. llvm-svn: 130313
* Be careful about scheduling nodes above previous calls. It increase usages ofEvan Cheng2011-04-262-1/+71
| | | | | | | | | | | | more callee-saved registers and introduce copies. Only allows it if scheduling a node above calls would end up lessen register pressure. Call operands also has added ABI restrictions for register allocation, so be extra careful with hoisting them above calls. rdar://9329627 llvm-svn: 130245
* This test should be in MC. It breaks with changes to scheduling / register ↵Evan Cheng2011-04-261-100/+0
| | | | | | allocation so it's being removed. llvm-svn: 130243
* don't emit the symbol name twice for local bss and commonChris Lattner2011-04-261-1/+1
| | | | | | | | | | | symbols. For example, don't emit: .comm _i,4,2 ## @i ## @i instead emit: .comm _i,4,2 ## @i llvm-svn: 130192
* Make this test disable fast isel as it's not needed.Eric Christopher2011-04-251-1/+1
| | | | llvm-svn: 130165
* Make tests more useful.Benjamin Kramer2011-04-251-1/+1
| | | | | | lit needs a linter ... llvm-svn: 130126
* Thumb2 and ARM add/subtract with carry fixes.Andrew Trick2011-04-231-0/+17
| | | | | | | | | | | | | Fixes Thumb2 ADCS and SBCS lowering: <rdar://problem/9275821>. t2ADCS/t2SBCS are now pseudo instructions, consistent with ARM, so the assembly printer correctly prints the 's' suffix. Fixes Thumb2 adde -> SBC matching to check for live/dead carry flags. Fixes the internal ARM machine opcode mnemonic for ADCS/SBCS. Fixes ARM SBC lowering to check for live carry (potential bug). llvm-svn: 130048
* Fix DWARF description of Q registers.Devang Patel2011-04-211-0/+94
| | | | llvm-svn: 129952
* Fix DWARF description of S registers.Devang Patel2011-04-211-0/+116
| | | | llvm-svn: 129947
* Test case for r129922Devang Patel2011-04-211-0/+105
| | | | llvm-svn: 129934
* Remove -use-divmod-libcall. Let targets opt in when they are available.Evan Cheng2011-04-201-1/+1
| | | | llvm-svn: 129884
* Rewrite the expander for umulo/smulo to remember to sign extend the inputEric Christopher2011-04-201-0/+27
| | | | | | | | | manually and pass all (now) 4 arguments to the mul libcall. Add a new ExpandLibCall for just this (copied gratuitously from type legalization). Fixes rdar://9292577 llvm-svn: 129842
* CodeGen: Eliminate a use of getDarwinMajorNumber().Daniel Dunbar2011-04-191-1/+1
| | | | | | | | | - There is a minor semantic change here (evidenced by the test change) for Darwin triples that have no version component. I debated changing the default behavior of isOSVersionLT, but decided it made more sense for triples to be explicit. llvm-svn: 129802
* This patch combines several changes from Evan Cheng for rdar://8659675.Bob Wilson2011-04-191-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Making use of VFP / NEON floating point multiply-accumulate / subtraction is difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Enable these fp vmlx codegen changes for Cortex-A9. llvm-svn: 129775
* Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson2011-04-191-8/+13
| | | | llvm-svn: 129774
* Avoid some 's' 16-bit instruction which partially update CPSRBob Wilson2011-04-191-0/+16
| | | | | | | (and add false dependency) when it isn't dependent on last CPSR defining instruction. rdar://8928208 llvm-svn: 129773
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-195-8/+8
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* Tighten test case a bit.Jakob Stoklund Olesen2011-04-191-1/+2
| | | | | | | Ideally, we would match an S-register to its containing D-register, but that requires arithmetic (divide by 2). llvm-svn: 129756
* Make tests register allocation independent again.Jakob Stoklund Olesen2011-04-192-3/+3
| | | | llvm-svn: 129739
* Do not lose mem_operands while lowering VLD / VST intrinsics.Evan Cheng2011-04-192-5/+7
| | | | llvm-svn: 129738
* Fix a bug where we were counting the alias sets as completely usedEric Christopher2011-04-181-0/+15
| | | | | | | | | registers for fast allocation a different way. This has us updating used registers only when we're using that exact register. Fixes rdar://9207598 llvm-svn: 129711
* Fix divmod libcall lowering. Convert to {S|U}DIVREM first and then expand ↵Evan Cheng2011-04-161-0/+31
| | | | | | the node to a libcall. rdar://9280991 llvm-svn: 129633
* Add ORR and EOR to the CMP peephole optimizer. It's hard to get isel to generateCameron Zwarich2011-04-151-3/+22
| | | | | | a case involving EOR, so I only added a test for ORR. llvm-svn: 129610
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