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* This change handles a another case for generating the bic instruction Joel Jones2012-06-181-0/+19
| | | | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. The 8 bit case doesn't need to be handled, as the 8 bit constants are encoded directly, thereby not needing a separate load instruction to form the constant into a register. <rdar://problem/11481151> llvm-svn: 158659
* ARM: optimization for sub+abs.Manman Ren2012-06-152-3/+21
| | | | | | | | | | | | | | This patch will optimize abs(x-y) FROM sub, movs, rsbmi TO subs, rsbmi For abs, we will use cmp instead of movs. This is necessary because we already have an existing peephole pass which optimizes away cmp following sub. rdar: 11633193 llvm-svn: 158551
* Preserve <undef> flags in ARMExpandPseudo.Jakob Stoklund Olesen2012-06-151-0/+8
| | | | | | This probably mostly shows up in bugpoint-generated code. llvm-svn: 158527
* Revert: test/CodeGen/ARM/iabs.ll in r158441Manman Ren2012-06-141-19/+1
| | | | | | Sorry that I accidently checked in this file with my previous commit. llvm-svn: 158442
* InstCombine: fix a bug when combining (fcmp cc0 x, y) && (fcmp cc1 x, y).Manman Ren2012-06-141-1/+19
| | | | | | uno && ueq was converted to ueq, it should be converted to uno. llvm-svn: 158441
* sched: fix latency of memory dependence chain edges for consistency.Andrew Trick2012-06-131-0/+41
| | | | | | | | | | | For store->load dependencies that may alias, we should always use TrueMemOrderLatency, which may eventually become a subtarget hook. In effect, we should guarantee at least TrueMemOrderLatency on at least one DAG path from a store to a may-alias load. This should fix the standard mode as well as -enable-aa-sched-mi". llvm-svn: 158380
* [arm-fast-isel] Add support for -arm-long-calls.Chad Rosier2012-06-122-0/+64
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 158368
* Fix test that depends on register allocation.Jakob Stoklund Olesen2012-06-111-5/+4
| | | | | | | The test is really checking the prolog/epilog load/store multiple formation. llvm-svn: 158328
* Re-enable the CMN instruction.Bill Wendling2012-06-111-0/+22
| | | | | | | | | We turned off the CMN instruction because it had semantics which we weren't getting correct. If we are comparing with an immediate, then it's okay to use the CMN instruction. <rdar://problem/7569620> llvm-svn: 158302
* Don't run RAFast in the optimizing regalloc pipeline.Jakob Stoklund Olesen2012-06-084-5/+5
| | | | | | | | | | | The fast register allocator is not supposed to work in the optimizing pipeline. It doesn't make sense to compute live intervals, run full copy coalescing, and then run RAFast. Fast register allocation in the optimizing pipeline is better done by RABasic. llvm-svn: 158242
* Revert commit r157966Joel Jones2012-06-051-19/+0
| | | | llvm-svn: 157972
* This change handles a another case for generating the bic instruction Joel Jones2012-06-041-0/+19
| | | | | | | | | when a compile time constant is known. This occurs when implicitly zero extending function arguments from 16 bits to 32 bits. <rdar://problem/11481151> llvm-svn: 157966
* Remove the "-promote-elements" flag. This flag is now enabled by default.Nadav Rotem2012-06-041-1/+1
| | | | llvm-svn: 157925
* ARM: add testing case for struct byvalManman Ren2012-06-021-0/+32
| | | | | | rdar://9877866 llvm-svn: 157876
* Make this testcase independent of register allocation.Owen Anderson2012-05-311-2/+2
| | | | llvm-svn: 157761
* Switch the canonical FMA term operand order to match both the comment I ↵Owen Anderson2012-05-301-1/+1
| | | | | | wrote and the usual LLVM convention. llvm-svn: 157708
* Teach DAGCombine to canonicalize the position of a constant in the term ↵Owen Anderson2012-05-301-0/+9
| | | | | | operands of an FMA node. llvm-svn: 157707
* [arm-fast-isel] Add support for the llvm.frameaddress() intrinsic.Chad Rosier2012-05-301-0/+100
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157696
* Teach taildup to update livein set. rdar://11538365Evan Cheng2012-05-301-0/+140
| | | | llvm-svn: 157663
* These tests used intrinsics with the wrong prototype. They weren't caught ↵Chris Lattner2012-05-271-15/+17
| | | | | | | | | because the old verifier just checked that something "was a pointer", but not that the pointee was correct. llvm-svn: 157544
* [arm-fast-isel] Add support for non-global callee.Chad Rosier2012-05-231-0/+20
| | | | | | Patch by Jush Lu <jush.msn@gmail.com>. llvm-svn: 157336
* revert my previous patches that introduced an additional parameter to the ↵Nuno Lopes2012-05-221-2/+2
| | | | | | | | objectsize intrinsic. After a lot of discussion, we realized it's not the best option for run-time bounds checking llvm-svn: 157255
* Transfer memory operands to the right instruction.Jakob Stoklund Olesen2012-05-201-4/+4
| | | | | | They need to go on the PICLDR as the verifier points out. llvm-svn: 157151
* Refactor data-in-code annotations.Jim Grosbach2012-05-181-0/+42
| | | | | | | | | | | | | | | | | | | | | | Use a dedicated MachO load command to annotate data-in-code regions. This is the same format the linker produces for final executable images, allowing consistency of representation and use of introspection tools for both object and executable files. Data-in-code regions are annotated via ".data_region"/".end_data_region" directive pairs, with an optional region type. data_region_directive := ".data_region" { region_type } region_type := "jt8" | "jt16" | "jt32" | "jta32" end_data_region_directive := ".end_data_region" The previous handling of ARM-style "$d.*" labels was broken and has been removed. Specifically, it didn't handle ARM vs. Thumb mode when marking the end of the section. rdar://11459456 llvm-svn: 157062
* Remove incorrect pattern for ARM SMML instruction.Tim Northover2012-05-171-0/+13
| | | | | | Patch by Meador Inge. llvm-svn: 156989
* Enable sub-sub-register copy coalescing.Jakob Stoklund Olesen2012-05-151-0/+68
| | | | | | | | | | | | | | | | It is now possible to coalesce weird skewed sub-register copies by picking a super-register class larger than both original registers. The included test case produces code like this: vld2.32 {d16, d17, d18, d19}, [r0]! vst2.32 {d18, d19, d20, d21}, [r0] We still perform interference checking as if it were a normal full copy join, so this is still quite conservative. In particular, the f1 and f2 functions in the included test case still have remaining copies because of false interference. llvm-svn: 156878
* [fast-isel] Add support for selecting @llvm.trap().Chad Rosier2012-05-111-0/+12
| | | | llvm-svn: 156646
* [fast-isel] Remove -disable-arm-fast-isel option. -fast-isel=0 suffices. ↵Chad Rosier2012-05-111-1/+1
| | | | | | Minor cleanup. llvm-svn: 156632
* [fast-isel] Cleaner fix for when we're unable to handle a non-double multi-regChad Rosier2012-05-111-0/+17
| | | | | | | | retval. Hoists check before emitting the call to avoid unnecessary work. rdar://11430407 PR12796 llvm-svn: 156628
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-111-0/+34
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156599
* Revert: 156550 "ARM: peephole optimization to remove cmp instruction"Manman Ren2012-05-101-34/+0
| | | | | | This commit broke an external linux bot and gave a compile-time warning. llvm-svn: 156556
* ARM: peephole optimization to remove cmp instructionManman Ren2012-05-101-0/+34
| | | | | | | | | | | | | | | | | This patch will optimize the following cases: sub r1, r3 | sub r1, imm cmp r3, r1 or cmp r1, r3 | cmp r1, imm bge L1 TO subs r1, r3 bge L1 or ble L1 If the branch instruction can use flag from "sub", then we can replace "sub" with "subs" and eliminate the "cmp" instruction. rdar: 10734411 llvm-svn: 156550
* change the objectsize intrinsic signature: add a 3rd parameter to denote the ↵Nuno Lopes2012-05-091-2/+2
| | | | | | | | maximum runtime performance penalty that the user is willing to accept. This commit only adds the parameter. Code taking advantage of it will follow. llvm-svn: 156473
* Teach DAG combine to fold x-x to 0.0 when unsafe FP math is enabled.Owen Anderson2012-05-071-0/+18
| | | | llvm-svn: 156324
* Teach DAGCombine the same multiply-by-1.0 folding trick when doing FMAs, ↵Owen Anderson2012-05-021-0/+9
| | | | | | just like it now knows for FMULs. llvm-svn: 156029
* Teach DAG combine that multiplication by 1.0 can always be constant folded.Owen Anderson2012-05-021-0/+9
| | | | llvm-svn: 156023
* Don't introduce illegal types when creating vmull operations. <rdar://11324364>Bob Wilson2012-04-301-0/+74
| | | | | | | | ARM BUILD_VECTORs created after type legalization cannot use i8 or i16 operands, since those types are not legal. Instead use i32 operands, which will be implicitly truncated by the BUILD_VECTOR to match the element type. llvm-svn: 155824
* Fix the order of the operands in the llvm.fma intrinsic patterns for ARM,Lang Hames2012-04-271-3/+3
| | | | | | <rdar://problem/11325085>. llvm-svn: 155724
* Implement a bastardized ABI.Evan Cheng2012-04-271-1/+0
| | | | llvm-svn: 155686
* Use VLD1 in NEON extenting-load patterns instead of VLDR.Tim Northover2012-04-261-2/+6
| | | | | | | On some cores it's a bad idea for performance to mix VFP and NEON instructions and since these patterns are NEON anyway, the NEON load should be used. llvm-svn: 155630
* MachineBasicBlock::SplitCriticalEdge() should follow LLVM IR variant and ↵Evan Cheng2012-04-241-0/+71
| | | | | | refuse to break edge to EH landing pad. rdar://11300144 llvm-svn: 155470
* Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.James Molloy2012-04-171-0/+14
| | | | llvm-svn: 154915
* FileCheckize these tests.Jakob Stoklund Olesen2012-04-162-6/+23
| | | | | | Add an extra test to ldr_post with an immediate increment. llvm-svn: 154859
* Disable code placement for this test.Jakob Stoklund Olesen2012-04-161-1/+2
| | | | | | It makes it less sensitive to small changes in heuristics. llvm-svn: 154857
* Flip the new block-placement pass to be on by default.Chandler Carruth2012-04-162-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | This is mostly to test the waters. I'd like to get results from FNT build bots and other bots running on non-x86 platforms. This feature has been pretty heavily tested over the last few months by me, and it fixes several of the execution time regressions caused by the inlining work by preventing inlining decisions from radically impacting block layout. I've seen very large improvements in yacr2 and ackermann benchmarks, along with the expected noise across all of the benchmark suite whenever code layout changes. I've analyzed all of the regressions and fixed them, or found them to be impossible to fix. See my email to llvmdev for more details. I'd like for this to be in 3.1 as it complements the inliner changes, but if any failures are showing up or anyone has concerns, it is just a flag flip and so can be easily turned off. I'm switching it on tonight to try and get at least one run through various folks' performance suites in case SPEC or something else has serious issues with it. I'll watch bots and revert if anything shows up. llvm-svn: 154816
* On Darwin targets, only use vfma etc. if the source use fma() intrinsic ↵Evan Cheng2012-04-131-1/+1
| | | | | | explicitly. llvm-svn: 154689
* Add more fused mul+add/sub patterns. rdar://10139676Evan Cheng2012-04-111-16/+54
| | | | llvm-svn: 154484
* Match (fneg (fma) to vfnma. rdar://10139676Evan Cheng2012-04-111-6/+25
| | | | llvm-svn: 154469
* Merge fma.ll into fusedMAC.llEvan Cheng2012-04-112-30/+28
| | | | llvm-svn: 154466
* Move the constant-folding support for FP_ROUND in SelectionDAG from the ↵Owen Anderson2012-04-101-18/+2
| | | | | | | | one-operand version of getNode() to the two-operand version, since it became a two-operand node at sound point. Zap a testcase that this allows us to completely fold away. llvm-svn: 154447
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