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* Eliminate some redundant llvm-as calls.Benjamin Kramer2009-10-121-1/+1
| | | | llvm-svn: 83837
* Update this test; the code is the same but it gets counted as oneDan Gohman2009-10-091-1/+1
| | | | | | fewer remat. llvm-svn: 83690
* Merge a bunch of NEON tests into larger files so they run faster.Bob Wilson2009-10-0987-3650/+3526
| | | | llvm-svn: 83667
* Convert some ARM tests with lots of greps to use FileCheck.Bob Wilson2009-10-095-58/+135
| | | | llvm-svn: 83651
* Commit one last NEON test to use FileCheck. That's all of them now!Bob Wilson2009-10-091-4/+13
| | | | llvm-svn: 83617
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-0911-115/+388
| | | | llvm-svn: 83616
* Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-091-0/+28
| | | | llvm-svn: 83600
* Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+28
| | | | llvm-svn: 83598
* Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+28
| | | | llvm-svn: 83596
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-089-46/+139
| | | | llvm-svn: 83595
* Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+53
| | | | | | Also fix some copy-and-paste errors in previous changes. llvm-svn: 83590
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-0813-100/+295
| | | | llvm-svn: 83587
* Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+47
| | | | llvm-svn: 83585
* Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via ↵Anton Korobeynikov2009-10-081-2/+2
| | | | | | movt/movw pair. llvm-svn: 83572
* Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.Bob Wilson2009-10-081-0/+41
| | | | llvm-svn: 83568
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-088-46/+140
| | | | llvm-svn: 83528
* Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+9
| | | | llvm-svn: 83526
* Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+9
| | | | llvm-svn: 83518
* Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-081-0/+9
| | | | llvm-svn: 83513
* Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+12
| | | | llvm-svn: 83508
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-076-35/+114
| | | | llvm-svn: 83507
* Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+12
| | | | llvm-svn: 83506
* Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.Bob Wilson2009-10-071-0/+12
| | | | llvm-svn: 83502
* Convert more NEON tests to use FileCheck.Bob Wilson2009-10-076-40/+118
| | | | llvm-svn: 83497
* Convert test to FileCheck.Bob Wilson2009-10-071-9/+27
| | | | llvm-svn: 83487
* Add codegen support for NEON vst4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+41
| | | | llvm-svn: 83486
* Add codegen support for NEON vst3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+41
| | | | llvm-svn: 83484
* Add codegen support for NEON vst2 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+37
| | | | llvm-svn: 83482
* Add codegen support for NEON vld4 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+54
| | | | llvm-svn: 83479
* Add codegen support for NEON vld3 intrinsics with 128-bit vectors.Bob Wilson2009-10-071-0/+54
| | | | llvm-svn: 83471
* Add tests for vld2 of 128-bit vectors.Bob Wilson2009-10-071-0/+50
| | | | llvm-svn: 83468
* Update NEON struct names to match llvm-gcc changes.Bob Wilson2009-10-068-195/+165
| | | | | | (This is not required for correctness but might help with sanity.) llvm-svn: 83415
* Fix tests.Evan Cheng2009-10-021-1/+1
| | | | llvm-svn: 83241
* Move load / store multiple before post-alloc scheduling.Evan Cheng2009-10-023-7/+5
| | | | llvm-svn: 83236
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-0112-24/+24
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Restore the -post-RA-scheduler flag as an override for the target ↵David Goodwin2009-10-015-5/+5
| | | | | | specification. Remove -mattr for setting PostRAScheduler enable and instead use CPU string. llvm-svn: 83215
* Remove -post-RA-schedule flag and add a TargetSubtarget method to enable ↵David Goodwin2009-09-305-5/+5
| | | | | | post-register-allocation scheduling. By default it is off. For ARM, enable/disable with -mattr=+/-postrasched. Enable by default for cortex-a8. llvm-svn: 83122
* Post-RA regressions.David Goodwin2009-09-295-4/+113
| | | | llvm-svn: 83075
* Fix PR4687. Pre ARMv5te does not support ldrd / strd. Patch by John Tytgat.Evan Cheng2009-09-291-0/+19
| | | | llvm-svn: 83058
* Coalescer should not delete extract_subreg, insert_subreg, and subreg_to_reg ofEvan Cheng2009-09-281-0/+24
| | | | | | | | | | | physical registers. This is especially critical for the later two since they start the live interval of a super-register. e.g. %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1 If this instruction is eliminated, the register scavenger will not be happy as D0 is not defined previously. This fixes PR5055. llvm-svn: 82968
* Use movt/movw pair to materialize 32 bit constants on ARMv6T2+.Anton Korobeynikov2009-09-271-0/+9
| | | | | | This should be better than single load from constpool. llvm-svn: 82948
* Remove this test.Evan Cheng2009-09-261-58/+0
| | | | llvm-svn: 82869
* "Update" tests for -disable-if-conversion removal. I think branch.ll should justDaniel Dunbar2009-09-261-0/+1
| | | | | | be removed, but I XFAIL'd it for now. llvm-svn: 82847
* Convert test to filecheck.Evan Cheng2009-09-261-3/+11
| | | | llvm-svn: 82835
* Flip -disable-post-RA-scheduler to -post-RA-scheduler.Evan Cheng2009-09-254-4/+4
| | | | llvm-svn: 82803
* Improve MachineMemOperand handling.Dan Gohman2009-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | - Allocate MachineMemOperands and MachineMemOperand lists in MachineFunctions. This eliminates MachineInstr's std::list member and allows the data to be created by isel and live for the remainder of codegen, avoiding a lot of copying and unnecessary translation. This also shrinks MemSDNode. - Delete MemOperandSDNode. Introduce MachineSDNode which has dedicated fields for MachineMemOperands. - Change MemSDNode to have a MachineMemOperand member instead of its own fields with the same information. This introduces some redundancy, but it's more consistent with what MachineInstr will eventually want. - Ignore alignment when searching for redundant loads for CSE, but remember the greatest alignment. Target-specific code which previously used MemOperandSDNodes with generic SDNodes now use MemIntrinsicSDNodes, with opcodes in a designated range so that the SelectionDAG framework knows that MachineMemOperand information is available. llvm-svn: 82794
* pr4926: ARM requires the stack pointer to be aligned, even for leaf functions.Bob Wilson2009-09-251-0/+17
| | | | | | | | | | | | | | | | | | | | For the AAPCS ABI, SP must always be 4-byte aligned, and at any "public interface" it must be 8-byte aligned. For the older ARM APCS ABI, the stack alignment is just always 4 bytes. For X86, we currently align SP at entry to a function (e.g., to 16 bytes for Darwin), but no stack alignment is needed at other times, such as for a leaf function. After discussing this with Dan, I decided to go with the approach of adding a new "TransientStackAlignment" field to TargetFrameInfo. This value specifies the stack alignment that must be maintained even in between calls. It defaults to 1 except for ARM, where it is 4. (Some other targets may also want to set this if they have similar stack requirements. It's not currently required for PPC because it sets targetHandlesStackFrameRounding and handles the alignment in target-specific code.) The existing StackAlignment value specifies the alignment upon entry to a function, which is how we've been using it anyway. llvm-svn: 82767
* Convert to FileCheck.Bob Wilson2009-09-241-4/+6
| | | | llvm-svn: 82710
* Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.Evan Cheng2009-09-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g. BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ... ... %reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool] ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose %reg1031<def> = FOO <cp#1>, %D0<imp-def> ... %S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill> When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness. Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead. llvm-svn: 82677
* Fix PR5024. LiveVariables physical register defs should *commit* only after allEvan Cheng2009-09-231-0/+23
| | | | | | | | of the defs are processed. Also fix a implicit_def propagation bug: a implicit_def of a physical register should be applied to uses of the sub-registers. llvm-svn: 82616
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