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* AArch64/ARM64: move ARM64 into AArch64's placeTim Northover2014-05-241-331/+0
| | | | | | | | | | | | | | | This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
* ARM64: use hex immediates for movz/movk instructionsTim Northover2014-04-301-1/+1
| | | | | | | | Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to piece together an immediate in 16-bit chunks, hex is probably the most appropriate format. llvm-svn: 207635
* ARM64: print canonical syntax for add/sub (imm) instructions.Tim Northover2014-04-301-8/+8
| | | | | | | | | | Since these instructions only accept a 12-bit immediate, possibly shifted left by 12, the canonical syntax used by the architecture reference manual is "#N {, lsl #12 }". We should accept an immediate that has already been shifted, (e.g. Also, print a comment giving the full addend since it can be helpful. llvm-svn: 207633
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-171-16/+8
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-171-16/+12
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). llvm-svn: 206490
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-161-9/+9
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. llvm-svn: 206379
* [ARM64] Set default CPU to generic instead of cyclone.Quentin Colombet2014-04-151-1/+1
| | | | llvm-svn: 206313
* ARM64: initial backend importTim Northover2014-03-291-0/+343
This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
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