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path: root/llvm/test/CodeGen/ARM/single-issue-r52.mir
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* [CodeGen] Use MIR syntax for MachineMemOperand printingFrancis Visoiu Mistrih2018-03-141-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-12/+12
* [CodeGen] Print RegClasses on MI in verbose modeFrancis Visoiu Mistrih2018-01-181-3/+3
* [CodeGen] Don't print "pred:" and "opt:" in -debug outputFrancis Visoiu Mistrih2018-01-091-3/+3
* [CodeGen] Don't print register classes in -debug outputFrancis Visoiu Mistrih2018-01-091-3/+3
* [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih2017-12-071-7/+7
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-4/+4
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-7/+7
* CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun2017-05-251-2/+2
* Improve machine schedulers for in-order processorsJaved Absar2017-03-271-0/+86
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