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* NFC - Various typo fixes in testsGabor Buella2018-07-041-1/+1
| | | | llvm-svn: 336268
* ARM: convert ORR instructions to ADD where possible on Thumb.Tim Northover2018-06-201-1/+1
| | | | | | | | | | | | Thumb has more 16-bit encoding space dedicated to ADD than ORR, allowing both a 3-address encoding and a wider range of immediates. So, particularly when optimizing for code size (but it doesn't make things worse elsewhere) it's beneficial to select an OR operation to an ADD if we know overflow won't occur. This is made even better by LLVM's penchant for putting operations in canonical form by converting the other way. llvm-svn: 335119
* [DAGCombine] Improve ReduceLoad for SRLSam Parker2018-04-091-4/+115
| | | | | | | | | | | | | Recommitting r329283, third time lucky... If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 llvm-svn: 329551
* [DAGCombine] Revert r329160Sam Parker2018-04-051-102/+4
| | | | | | Again, broke the big endian stage 2 builders. llvm-svn: 329283
* [DAGCombine] Improve ReduceLoadWidth for SRLSam Parker2018-04-041-4/+102
| | | | | | | | | | | | | | | | | | Recommitting rL321259. Previosuly this caused an issue with PPCBE but I didn't receieve a reproducer and didn't have the time to follow up. If the issue appears again, please provide a reproducer so I can fix it. Original commit message: If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 llvm-svn: 329160
* [DAGCombine] Revert r321259Sam Parker2017-12-221-102/+4
| | | | | | | Improve ReduceLoadWidth for SRL Patch is causing an issue on the PPC64 BE santizer. llvm-svn: 321349
* [DAGCombine] Improve ReduceLoadWidth for SRLSam Parker2017-12-211-4/+102
| | | | | | | | | | | If the SRL node is only used by an AND, we may be able to set the ExtVT to the width of the mask, making the AND redundant. To support this, another check has been added in isLegalNarrowLoad which queries whether the load is valid. Differential Revision: https://reviews.llvm.org/D41350 llvm-svn: 321259
* [ARM] Adjust test checksSam Parker2017-12-181-2/+2
| | | | | | Correct the CHECK-LABELS of a couple of dag combine tests. llvm-svn: 320963
* [ARM] Some DAG combine testsSam Parker2017-12-151-0/+57
| | | | | | Add some more and and shift load combine tests. llvm-svn: 320822
* [DAGCombine] Enable more srl -> load combinesSam Parker2017-11-161-10/+198
| | | | | | | | | | | | Change the calculation for the desired ValueType for non-sign extending loads, as in those cases we don't care about the higher bits. This creates a smaller ExtVT and allows for such combinations as: (srl (zextload i16, [addr]), 8) -> (zextload i8, [addr + 1]) Differential Revision: https://reviews.llvm.org/D40034 llvm-svn: 318390
* Make the canonicalisation on shifts benifit to more case.Zijiao Ma2016-12-231-0/+31
1.Fix pessimized case in FIXME. 2.Add tests for it. 3.The canonicalisation on shifts results in different sequence for tests of machine-licm.Correct some check lines. Differential Revision: https://reviews.llvm.org/D27916 llvm-svn: 290410
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