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* [DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies with 0 to 0 and ↵Craig Topper2019-09-081-2/+2
| | | | | | | | | no carry. I modified the ARM test to use two inputs instead of 0 so the test hopefully still tests what was intended. llvm-svn: 371344
* [ARM] Favour PL/MI over GE/LT when possibleDavid Green2019-07-041-2/+2
| | | | | | | | | | | | | | | The arm condition codes for GE is N==V (and for LT is N!=V). If the source of flags cannot set V (overflow), such as a cmp against #0, then we can use the simpler PL and MI conditions that only check N. As these PL/MI conditions are simpler than GE/LT, other passes like the peephole optimiser can have a better time optimising away the redundant CMPs. The exception is the VSEL instruction, which cannot take the PL code, so there the transform favours GE. Differential Revision: https://reviews.llvm.org/D64160 llvm-svn: 365117
* ARM: use target-specific SUBS node when combining cmp with cmov.Tim Northover2018-12-031-0/+11
| | | | | | | | | | | This has two positive effects. First, using a custom node prevents recombination leading to an infinite loop since the output DAG is notionally a little more complex than the input one. Using a flag-setting instruction also allows the subtraction to be folded with the related comparison more easily. https://reviews.llvm.org/D53190 llvm-svn: 348122
* [SchedModel] Fix for read advance cycles with implicit pseudo operands.Jonas Paulsson2018-10-301-1/+1
| | | | | | | | | | | | | | | | | | The SchedModel allows the addition of ReadAdvances to express that certain operands of the instructions are needed at a later point than the others. RegAlloc may add pseudo operands that are not part of the instruction descriptor, and therefore cannot have any read advance entries. This meant that in some cases the desired read advance was nullified by such a pseudo operand, which still had the original latency. This patch fixes this by making sure that such pseudo operands get a zero latency during DAG construction. Review: Matthias Braun, Ulrich Weigand. https://reviews.llvm.org/D49671 llvm-svn: 345606
* Revert "[ARM] Lower lower saturate to 0 and lower saturate to -1 using ↵Evgeniy Stepanov2018-01-311-1/+1
| | | | | | | | | | bit-operations" Miscompiles code. Testcase pending. This reverts commit r323869. llvm-svn: 323929
* [ARM] Lower lower saturate to 0 and lower saturate to -1 using bit-operationsPablo Barrio2018-01-311-1/+1
| | | | | | | | | | | | | | | | | | | Summary: Expressions of the form x < 0 ? 0 : x; and x < -1 ? -1 : x can be lowered using bit-operations instead of branching or conditional moves In thumb-mode this results in a two-instruction sequence, a shift followed by a bic or or while in ARM/thumb2 mode that has flexible second operand the shift can be folded into a single bic/or instructions. In most cases this results in smaller code and possibly less branches, and in no case larger than before. Patch by Marten Svanfeldt. Reviewers: fhahn, pbarrio Reviewed By: pbarrio Subscribers: efriedma, rogfer01, aemerson, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D42574 llvm-svn: 323869
* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-031-3/+7
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
* Revert "Tests: Be less dependent on a specific schedule/regalloc"Matthias Braun2013-10-111-5/+5
| | | | | | | | | This reverts r192454 Apparently FileCheck isn't as smart as I though and does not enforce a topological order between variable defs+uses. llvm-svn: 192472
* Tests: Be less dependent on a specific schedule/regallocMatthias Braun2013-10-111-5/+5
| | | | llvm-svn: 192454
* Tests: Use CHECK-LABEL where possibleMatthias Braun2013-10-101-4/+4
| | | | llvm-svn: 192403
* ARM: use TableGen patterns to select CMOV operations.Tim Northover2013-08-221-1/+1
| | | | | | | | | | | | Back in the mists of time (2008), it seems TableGen couldn't handle the patterns necessary to match ARM's CMOV node that we convert select operations to, so we wrote a lot of fairly hairy C++ to do it for us. TableGen can deal with it now: there were a few minor differences to CodeGen (see tests), but nothing obviously worse that I could see, so we should probably address anything that *does* come up in a localised manner. llvm-svn: 188995
* Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to ↵Stephen Lin2013-07-141-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
* Use predication instead of pseudo-opcodes when folding into MOVCC.Jakob Stoklund Olesen2012-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | Now that it is possible to dynamically tie MachineInstr operands, predicated instructions are possible in SSA form: %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR Becomes a predicated SUBri with a tied imp-use: SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0> This means that any instruction that is safe to move can be folded into a MOVCC, and the *CC pseudo-instructions are no longer needed. The test case changes reflect that Thumb2SizeReduce recognizes the predicated instructions. It didn't understand the pseudos. llvm-svn: 163274
* Add ADD and SUB to the predicable ARM instructions.Jakob Stoklund Olesen2012-08-161-4/+3
| | | | | | | | | | It is not my plan to duplicate the entire ARM instruction set with predicated versions. We need a way of representing predicated instructions in SSA form without requiring a separate opcode. Then the pseudo-instructions can go away. llvm-svn: 162061
* Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional ↵Owen Anderson2012-07-091-0/+26
| | | | | | | | move, since there are only two possible values. Previously, this would become an integer extension operation, followed by a real integer->float conversion. llvm-svn: 159957
* Allocate virtual registers in ascending order.Jakob Stoklund Olesen2012-04-021-5/+5
| | | | | | | | | This is just the fallback tie-breaker ordering, the main allocation order is still descending size. Patch by Shamil Kurmangaleev! llvm-svn: 153904
* Fix SimplifySelectCC to add newly created nodes to the DAGCombinerDan Gohman2011-09-221-6/+6
| | | | | | worklist, as it may be possible to perform further optimization on them. llvm-svn: 140349
* Thumb assembly parsing and encoding for ADR.Jim Grosbach2011-08-171-1/+1
| | | | llvm-svn: 137864
* Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.Bob Wilson2011-03-081-0/+23
| | | | llvm-svn: 127198
* These tests are looking for library function names thatDale Johannesen2010-11-171-1/+1
| | | | | | | appear to differ on Linux. Try to make them pass on Linux. Would be good for a Linux person to review this. llvm-svn: 119572
* - Add TargetInstrInfo::getOperandLatency() to compute operand latencies. ThisEvan Cheng2010-10-061-1/+1
| | | | | | | | | | | | | allow target to correctly compute latency for cases where static scheduling itineraries isn't sufficient. e.g. variable_ops instructions such as ARM::ldm. This also allows target without scheduling itineraries to compute operand latencies. e.g. X86 can return (approximated) latencies for high latency instructions such as division. - Compute operand latencies for those defined by load multiple instructions, e.g. ldm and those used by store multiple instructions, e.g. stm. llvm-svn: 115755
* Consider this code snippet:Bill Wendling2010-08-111-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | float t1(int argc) { return (argc == 1123) ? 1.234f : 2.38213f; } We would generate truly awful code on ARM (those with a weak stomach should look away): _t1: movw r1, #1123 movs r2, #1 movs r3, #0 cmp r0, r1 mov.w r0, #0 it eq moveq r0, r2 movs r1, #4 cmp r0, #0 it ne movne r3, r1 adr r0, #LCPI1_0 ldr r0, [r0, r3] bx lr The problem was that legalization was creating a cascade of SELECT_CC nodes, for for the comparison of "argc == 1123" which was fed into a SELECT node for the ?: statement which was itself converted to a SELECT_CC node. This is because the ARM back-end doesn't have custom lowering for SELECT nodes, so it used the default "Expand". I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this testcase, but can obviously be expanded to include more cases. Now we generate this, which looks optimal to me: _t1: movw r1, #1123 movs r2, #0 cmp r0, r1 adr r0, #LCPI0_0 it eq moveq r2, #4 ldr r0, [r0, r2] bx lr .align 2 LCPI0_0: .long 1075344593 @ float 2.382130e+00 .long 1067316150 @ float 1.234000e+00 llvm-svn: 110799
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-1/+1
| | | | llvm-svn: 86494
* Convert some ARM tests with lots of greps to use FileCheck.Bob Wilson2009-10-091-8/+19
| | | | llvm-svn: 83651
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-7/+7
| | | | llvm-svn: 81293
* Move thumb and thumb2 tests into separate directories.Evan Cheng2009-06-241-7/+0
| | | | llvm-svn: 74068
* Convert tests using "| wc -l | grep ..." to use the count script.Dan Gohman2007-08-151-13/+13
| | | | llvm-svn: 41097
* For PR1319: Upgrade to use new test harnessReid Spencer2007-04-151-14/+14
| | | | llvm-svn: 36076
* -march=arm -enable-thumb => -march=thumbEvan Cheng2007-02-231-7/+7
| | | | llvm-svn: 34522
* For PR761:Reid Spencer2007-01-261-7/+7
| | | | | | | | | | | | | | Remove "target endian/pointersize" or add "target datalayout" to make the test parse properly or set the datalayout because defaults changes. For PR645: Make global names use the @ prefix. For llvm-upgrade changes: Fix test cases or completely remove use of llvm-upgrade for test cases that cannot survive the new renaming or upgrade capabilities. llvm-svn: 33533
* ARM test cases contributed by Apple.Evan Cheng2007-01-191-31/+45
| | | | llvm-svn: 33354
* Regression is gone, don't try to find it on clean target.Reid Spencer2007-01-171-0/+49
llvm-svn: 33296
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