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* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2020-02-081-180/+0
| | | | This reverts commit 60e0120c913dd1d4bfe33769e1f000a076249a42.
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2020-01-071-0/+180
| | | | | | | | | | | | | | | | | | Summary: Instead of generating two i32 instructions for each load or store of a volatile i64 value (two LDRs or STRs), now emit LDRD/STRD. These improvements cover architectures implementing ARMv5TE or Thumb-2. Reviewers: dmgreen, efriedma, john.brawn, nickdesaulniers Reviewed By: efriedma, nickdesaulniers Subscribers: nickdesaulniers, vvereschaka, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70072
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-201-153/+0
| | | | This reverts commit bbcf1c3496ce2bd1ed87e8fb15ad896e279633ce.
* [ARM] Improve codegen of volatile load/store of i64Victor Campos2019-12-191-0/+153
Summary: Instead of generating two i32 instructions for each load or store of a volatile i64 value (two LDRs or STRs), now emit LDRD/STRD. These improvements cover architectures implementing ARMv5TE or Thumb-2. Reviewers: dmgreen, efriedma, john.brawn Reviewed By: efriedma Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D70072
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