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* ARM: fixup more tests to specify the target more explicitlySaleem Abdulrasool2014-04-031-6/+17
| | | | | | | | | | | | | This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier ↵Stephen Lin2013-07-131-8/+8
| | | | | | | | | | debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
* Fix Darwin NEON FP and increase coverageRenato Golin2013-03-211-2/+3
| | | | llvm-svn: 177664
* Avoid NEON SP-FP unless unsafe-math or DarwinRenato Golin2013-03-211-1/+2
| | | | | | | | | | NEON is not IEEE 754 compliant, so we should avoid lowering single-precision floating point operations with NEON unless unsafe-math is turned on. The equivalent VFP instructions are IEEE 754 compliant, but in some cores they're much slower, so some archs/OSs might still request it to be on by default, such as Swift and Darwin. llvm-svn: 177651
* Add LLVM support for Swift.Bob Wilson2012-09-291-2/+2
| | | | llvm-svn: 164899
* Inflate register classes after coalescing.Jakob Stoklund Olesen2011-08-091-2/+4
| | | | | | | | | | | | | | | | | | | | | | | Coalescing can remove copy-like instructions with sub-register operands that constrained the register class. Examples are: x86: GR32_ABCD:sub_8bit_hi -> GR32 arm: DPR_VFP2:ssub0 -> DPR Recompute the register class of any virtual registers that are used by less instructions after coalescing. This affects code generation for the Cortex-A8 where we use NEON instructions for f32 operations, c.f. fp_convert.ll: vadd.f32 d16, d1, d0 vcvt.s32.f32 d0, d16 The register allocator is now free to use d16 for the temporary, and that comes first in the allocation order because it doesn't interfere with any s-registers. llvm-svn: 137133
* Avoid write-after-write issue hazards for Cortex-A9.Bob Wilson2011-04-191-4/+4
| | | | | | | | | | | Add a avoidWriteAfterWrite() target hook to identify register classes that suffer from write-after-write hazards. For those register classes, try to avoid writing the same register in two consecutive instructions. This is currently disabled by default. We should not spill to avoid hazards! The command line flag -avoid-waw-hazard can be used to enable waw avoidance. llvm-svn: 129772
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-251-2/+1
| | | | | | Re-commit. This time complete with testsuite updates. llvm-svn: 99570
* Use Unified Assembly Syntax for the ARM backend.Jim Grosbach2009-11-091-4/+4
| | | | llvm-svn: 86494
* Remove neonfp attribute and instead set default based on CPU string. Add ↵David Goodwin2009-10-011-2/+2
| | | | | | -arm-use-neon-fp to override the default. llvm-svn: 83218
* Eliminate more uses of llvm-as and llvm-dis.Dan Gohman2009-09-091-5/+5
| | | | llvm-svn: 81293
* now that these are in file-check format, we can merge them togetherChris Lattner2009-08-111-0/+49
into one bigger test (which runs faster) llvm-svn: 78672
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